Patents by Inventor Codrut Radu Radulescu

Codrut Radu Radulescu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240062296
    Abstract: A method for synchronous processing, comprising a list of tasks for a first time period, a second list of tasks for a second time period and processing the first list during the second time period.
    Type: Application
    Filed: October 2, 2023
    Publication date: February 22, 2024
    Inventor: Codrut Radu Radulescu
  • Patent number: 11776053
    Abstract: A method for synchronous processing exchange orders, comprising: creating a first batch of orders by accumulating exchange orders received within a first time period, TP1; creating a second batch of orders by accumulating exchange orders received within a second time period, TP2; and processing the orders from the first batch within the second time period, TP2.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: October 3, 2023
    Inventor: Codrut Radu Radulescu
  • Publication number: 20170330278
    Abstract: A method for synchronous processing exchange orders, comprising: creating a first batch of orders by accumulating exchange orders received within a first time period, TP1; creating a second batch of orders by accumulating exchange orders received within a second time period, TP2; and processing the orders from the first batch within the second time period, TP2.
    Type: Application
    Filed: September 8, 2015
    Publication date: November 16, 2017
    Inventor: Codrut Radu RADULESCU
  • Patent number: 8467313
    Abstract: The present invention provides a system and method of determining available bandwidth at a physical layer (PHY) device at a server on a broadband network. A link layer controller of a master administrator adaptively polls a PHY device over a set of time intervals. During polling, the controller places a PHY device's address on a line of a bus and awaits a response from the PHY device. Based upon the response from the PHY device, the administrator can determine whether the PHY device has available bandwidth. The link layer controller uses this information to recalculate its polling scheme to better make use of the available bandwidth over the shared transmission medium to which each PHY device in the network is attached.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: June 18, 2013
    Inventor: Codrut Radu Radulescu
  • Patent number: 8416812
    Abstract: A method and means synchronize timing of a follower system to a reference system. A Hierarchical CFF function (“HCFF”) is applied to a set of Correction Factor Functions types (“CFFs”) or a set of other HCFF. Each CFF type uses the same input data set specific to that type and generates at least one Correction Factor Solution (“CFS”) for each of the CFF, wherein the CFS consists of only CF or the CFS consists of both i) CF and ii) a SACF. The HCFF takes as input a set of CFS and generates at least one CFS, wherein the CFS consist of only the CF, or the CFS consists of both the i) CF and ii) a SACF.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: April 9, 2013
    Inventor: Codrut Radu Radulescu
  • Patent number: 7924857
    Abstract: A method and apparatus of reorganizing cells received over data communication lines at a receive node is provided. The cells have an initial order identified by monotonically increasing sequence identifiers. The receive node has buffers associated with respective ones of the communication lines. Each of the buffers has an output position. A cell having a smallest sequence identifier is detected from one or more cells at the output positions of the buffers. It is determined if the smallest sequence identifier is sequentially consecutive to a specified sequence identifier. If the smallest sequence identifier is sequentially consecutive to the specified sequence identifier, the cell having the smallest sequence identifier is dequeued from an output position of one of the buffers and the specified sequence identifier is redefined as the smallest sequence identifier.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: April 12, 2011
    Assignee: Agere Systems Inc.
    Inventors: Deepak Kataria, Codrut Radu Radulescu
  • Patent number: 7839897
    Abstract: Methods and apparatus for synchronizing a first clock of a transmit node and a second clock of receive node in a packet network are provided. Consecutive intervals of time-stamped packets transferred from the transmit node to the receive node are selected. The consecutive intervals have a difference in delay noise within a defined acceptance window. A correction factor is determined for the second clock in accordance with transmit and receive time stamps of transferred time-stamped packets bounding the consecutive intervals. The correction factor is applied to the second clock to synchronize the second clock of the receive node with the first clock of the transmit node.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: November 23, 2010
    Assignee: Agere Systems Inc.
    Inventor: Codrut Radu Radulescu
  • Publication number: 20100118895
    Abstract: A method and means synchronize timing of a follower system to a reference system. A Hierarchical CFF function (“HCFF”) is applied to a set of Correction Factor Functions types (“CFFs”) or a set of other HCFF. Each CFF type uses the same input data set specific to that type and generates at least one Correction Factor Solution (“CFS”) for each of the CFF, wherein the CFS consists of only CF or the CFS consists of both i) CF and ii) a SACF. The HCFF takes as input a set of CFS and generates at least one CFS, wherein the CFS consist of only the CF, or the CFS consists of both the i) CF and ii) a SACF.
    Type: Application
    Filed: September 21, 2009
    Publication date: May 13, 2010
    Inventor: Codrut Radu Radulescu
  • Patent number: 7633962
    Abstract: A method of minimizing SID difference of simultaneously transmitted cells in two or more data communication lines is provided. A data transmission speed of each of the two or more data communication lines is identified. A fullness threshold of at least one buffer of two or more buffers in a transmit node is configured in relation to a size of a data cell for transmission. The two or more buffers correspond to respective ones of the two or more data communication lines. The at least one buffer communicates with a given one of the two or more data communication lines having a data transmission speed slower than another of the two or more data communication lines. One or more data cells for transmission are assigned to the two or more buffers of the two or more data communication lines at the transmit node. The one or more data cells are transmitted from the transmit node to a receive node in accordance with the data transmission speeds of the two or more data communication lines.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: December 15, 2009
    Assignee: Agere Systems Inc.
    Inventors: Deepak Kataria, Codrut Radu Radulescu
  • Publication number: 20090073889
    Abstract: The present invention provides a system and method of determining available bandwidth at a physical layer (PHY) device at a server on a broadband network. A link layer controller of a master administrator adaptively polls a PHY device over a set of time intervals. During polling, the controller places a PHY device's address on a line of a bus and awaits a response from the PHY device. Based upon the response from the PHY device, the administrator can determine whether the PHY device has available bandwidth. The link layer controller uses this information to recalculate its polling scheme to better make use of the available bandwidth over the shared transmission medium to which each PHY device in the network is attached.
    Type: Application
    Filed: September 19, 2007
    Publication date: March 19, 2009
    Applicant: AGERE SYSTEMS INC.
    Inventor: Codrut Radu Radulescu
  • Publication number: 20080080567
    Abstract: Methods and apparatus for synchronizing a first clock of a transmit node and a second clock of receive node in a packet network are provided. Consecutive intervals of time-stamped packets transferred from the transmit node to the receive node are selected. The consecutive intervals have a difference in delay noise within a defined acceptance window. A correction factor is determined for the second clock in accordance with transmit and receive time stamps of transferred time-stamped packets bounding the consecutive intervals. The correction factor is applied to the second clock to synchronize the second clock of the receive node with the first clock of the transmit node.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventor: Codrut Radu Radulescu