Patents by Inventor Colby G. Rampley
Colby G. Rampley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9111983Abstract: Various embodiments of semiconductor manufacturing methods include releasing a transparent carrier from a semiconductor wafer assembly that includes a semiconductor wafer in which a plurality of semiconductor devices are formed, an adhesive layer coupled to the semiconductor wafer, a carrier release layer coupled to the adhesive layer, and the transparent carrier coupled to the carrier release layer. The method further includes controlling a laser system to emit a first beam characterized by first laser parameters toward the adhesive layer, where the first laser parameters are selected so that the first beam will compromise a physical integrity of the adhesive layer. The method further includes, after controlling the laser system to emit the first beam toward the adhesive layer, removing the adhesive layer from the semiconductor wafer.Type: GrantFiled: July 31, 2014Date of Patent: August 18, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Kevin P. Ginter, Colby G. Rampley, Jeffrey L. Weibrecht
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Publication number: 20140238483Abstract: A nano-scale tower structure array having increased surface area on each tower for gathering incident light is provided for use in three-dimensional solar cells. Embodiments enhance surface roughness of each tower structure to increase the surface area available for light gathering. Enhanced roughness can be provided by manipulating passivation layer etching parameters used during a formation process of the nano-scale tower structures, in order to affect surface roughness of a photoresist layer used for the etch. Manipulable etching parameters can include power, gas pressure, and etching compound chemistry.Type: ApplicationFiled: May 6, 2014Publication date: August 28, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: COLBY G. RAMPLEY, Frank T. Laver, Thomas E. Wood
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Publication number: 20140232017Abstract: A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.Type: ApplicationFiled: April 28, 2014Publication date: August 21, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: COLBY G. RAMPLEY, LAWRENCE S. KLINGBEIL
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Patent number: 8790947Abstract: A nano-scale tower structure array having increased surface area on each tower for gathering incident light is provided for use in three-dimensional solar cells. Embodiments enhance surface roughness of each tower structure to increase the surface area available for light gathering. Enhanced roughness can be provided by manipulating passivation layer etching parameters used during a formation process of the nano-scale tower structures, in order to affect surface roughness of a photoresist layer used for the etch. Manipulable etching parameters can include power, gas pressure, and etching compound chemistry.Type: GrantFiled: October 13, 2011Date of Patent: July 29, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Colby G. Rampley, Frank T. Laver, Thomas E. Wood
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Patent number: 8742599Abstract: A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.Type: GrantFiled: August 30, 2012Date of Patent: June 3, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Colby G. Rampley, Lawrence S. Klingbeil
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Publication number: 20140061952Abstract: A method and system for uniquely identifying each semiconductor device die from a wafer is provided. Identifying features are associated with device die bond pads. In one embodiment, one or more tab features are patterned and associated with each of one or more device die bond pads. These features can represent a code (e.g., binary or ternary) that uniquely identifies each device die on the wafer. Each tab feature can be the same shape or different shapes, depending upon the nature of coding desired. Alternatively, portions of the one or more device die bond pads can be omitted as a mechanism for providing coded information, rather than adding portions to the device die bond pads.Type: ApplicationFiled: August 30, 2012Publication date: March 6, 2014Inventors: Colby G. Rampley, Lawrence S. Klingbeil
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Publication number: 20130092223Abstract: A nano-scale tower structure array having increased surface area on each tower for gathering incident light is provided for use in three-dimensional solar cells. Embodiments enhance surface roughness of each tower structure to increase the surface area available for light gathering. Enhanced roughness can be provided by manipulating passivation layer etching parameters used during a formation process of the nano-scale tower structures, in order to affect surface roughness of a photoresist layer used for the etch. Manipulable etching parameters can include power, gas pressure, and etching compound chemistry.Type: ApplicationFiled: October 13, 2011Publication date: April 18, 2013Inventors: Colby G. Rampley, Frank T. Laver, Thomas E. Wood
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Patent number: 6893947Abstract: A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating (105) an implant region (36, 37) in the unmasked region, and (b) removing (107) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.Type: GrantFiled: June 25, 2002Date of Patent: May 17, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Marino J. Martinez, Ernest Schirmann, Olin L. Hartin, Colby G. Rampley, Mariam G. Sadaka, Charles E. Weitzel, Julio Costa
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Patent number: 6798064Abstract: An electronic component includes a substrate (110) and an airbridge (890) located over the substrate. The airbridge has at least a first layer and a second layer over the first layer. The airbridge is electrically conductive where the first layer of the airbridge is less resistive than the second layer of the airbridge.Type: GrantFiled: July 12, 2000Date of Patent: September 28, 2004Assignee: Motorola, Inc.Inventors: Haldane S. Henry, Darrell G. Hill, Colby G. Rampley
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Publication number: 20030235974Abstract: A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating (105) an implant region (36, 37) in the unmasked region, and (b) removing (107) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.Type: ApplicationFiled: June 25, 2002Publication date: December 25, 2003Applicant: Motorola Inc.Inventors: Marino J. Martinez, Ernest Schirmann, Olin L. Hartin, Colby G. Rampley, Mariam G. Sadaka, Charles E. Weitzel, Julio Costa