Patents by Inventor Colby RAMPLEY

Colby RAMPLEY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10014262
    Abstract: Method embodiments of wafer dicing for backside metallization are provided. One method includes: applying dicing tape to a front side of a semiconductor wafer, wherein the front side of the semiconductor wafer includes active circuitry; cutting a back side of the semiconductor wafer, the back side opposite the front side, wherein the cutting forms a retrograde cavity in a street of the semiconductor wafer, the retrograde cavity has a gap width at the back side of the semiconductor wafer, and the retrograde cavity has sidewalls with negative slope; depositing a metal layer on the back side of the semiconductor wafer, wherein the gap width is large enough to prevent formation of the metal layer over the retrograde cavity; and cutting through the street of the semiconductor wafer subsequent to the depositing the metal layer.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: July 3, 2018
    Assignee: NXP USA, Inc.
    Inventors: L. Scott Klingbeil, Colby Rampley
  • Patent number: 9941210
    Abstract: An embodiment of a semiconductor die includes a base semiconductor substrate and an electrically conductive through substrate via (TSV) extending between the surfaces of the base semiconductor substrate. The bottom surface of the base semiconductor substrate includes a recessed region proximate to the TSV so that an end of the TSV protrudes from the bottom surface, and so that the TSV sidewall has an exposed portion at the protruding end of the TSV. Back metal, consisting of one or more metallic layers, is deposited on the bottom surface of the base semiconductor substrate and in contact with the TSV. The back metal can include a gold layer, a sintered metallic layer, and/or a plurality of other conductive layers. The die may be attached to a substrate using solder, another sintered metallic layer, or other materials.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: April 10, 2018
    Assignee: NXP USA, INC.
    Inventors: Lakshminarayan Viswanathan, Jaynal A. Molla, Mali Mahalingam, Colby Rampley
  • Publication number: 20170358537
    Abstract: Method embodiments of wafer dicing for backside metallization are provided. One method includes: applying dicing tape to a front side of a semiconductor wafer, wherein the front side of the semiconductor wafer includes active circuitry; cutting a back side of the semiconductor wafer, the back side opposite the front side, wherein the cutting forms a retrograde cavity in a street of the semiconductor wafer, the retrograde cavity has a gap width at the back side of the semiconductor wafer, and the retrograde cavity has sidewalls with negative slope; depositing a metal layer on the back side of the semiconductor wafer, wherein the gap width is large enough to prevent formation of the metal layer over the retrograde cavity; and cutting through the street of the semiconductor wafer subsequent to the depositing the metal layer.
    Type: Application
    Filed: June 14, 2016
    Publication date: December 14, 2017
    Inventors: L. Scott KLINGBEIL, Colby RAMPLEY