Patents by Inventor Cole D. Wilson

Cole D. Wilson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10352975
    Abstract: A contact's interaction with a sensing array is subject to several external and internal stimuli which may impact a processing unit's confidence in the characteristics of that interaction or the presence of the interaction itself. Fidelity of user action is greatly improved with a step-wise and holistic analysis of a contact on an array of capacitance sensors, which allows for repetition of certain steps of processing or the entire operation if threshold confidence levels are not achieved.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: July 16, 2019
    Assignee: PARADE TECHNOLOGIES, LTD.
    Inventors: Jonathan R Peterson, Cole D Wilson, David G Wright
  • Patent number: 10338739
    Abstract: A method and apparatus to determine a plurality of regions, each of the plurality of regions having a detected change in sensor value that meets or exceeds a threshold value, fit a three dimensional shape to the plurality of regions, and determine a position of an object.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 2, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jonathan R Peterson, Cole D. Wilson, Thomas Fuller, Derek James Valleroy
  • Patent number: 10073563
    Abstract: An electronic system includes a processing device and a trellis pattern of conductors coupled to the processing device. The trellis pattern of conductors forms a multiple capacitors and the processing device is configured to sense a capacitance of each of the capacitors. A host is coupled to the processing device. The host includes decision logic to determine a state of the trellis pattern of conductors responsive to a signal that indicates a capacitance of one or more capacitors sensed by the processing device.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: September 11, 2018
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Cole D. Wilson, Patrick N Prendergast, Jonathan R Peterson
  • Patent number: 9829523
    Abstract: A capacitive sensor array may comprise a plurality of column sensor electrodes and a plurality of row sensor electrodes. The column sensor electrodes may be capacitively coupled with the row sensor electrodes to form a plurality of unit cells each including an intensity center identifying a location of greatest capacitance sensitivity between a row electrode and a column electrode. An axis of a set of row sensor electrodes may cross at least a portion of each row electrode in the set, and the intensity centers associated with the row electrodes in the set may be staggered on alternating sides of the axis. For each of the plurality of unit cells, a distance between the intensity center of the unit cell and a nearest intensity center of another unit cell at a perimeter of the unit cell may be at least 0.7 times the height of the unit cell.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: November 28, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jonathan R Peterson, Cole D Wilson, Patrick N Prendergast
  • Publication number: 20170017347
    Abstract: An electronic system includes a processing device and a trellis pattern of conductors coupled to the processing device. The trellis pattern of conductors forms a multiple capacitors and the processing device is configured to sense a capacitance of each of the capacitors. A host is coupled to the processing device.
    Type: Application
    Filed: July 26, 2016
    Publication date: January 19, 2017
    Inventors: Cole D. Wilson, Patrick N Prendergast, Jonathan R Peterson
  • Patent number: 9519391
    Abstract: Embodiments described herein provide capacitive sensor arrays. The capacitive sensor arrays include a plurality of column sensor elements arranged in a plurality of columns and a plurality of row sensor elements arranged in a plurality of rows. The plurality of rows and the plurality of columns are arranged such that each of the row sensor elements is at least partially within a gap between adjacent ones of the column sensor elements. A capacitance between a first portion of one of the columns and an adjacent first portion of one of the rows is greater than a capacitance between a second portion of one of the columns and an adjacent second portion of one of the rows.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: December 13, 2016
    Assignee: MONTEREY RESEARCH, LLC
    Inventors: Jonathan R Peterson, Cole D. Wilson
  • Patent number: 9436339
    Abstract: A capacitive sensor array includes a second sensor element intersecting a first sensor element to form an intersection associated with a unit cell. The second sensor element includes, within the unit cell: a first primary trace crossing the unit cell and a second primary trace crossing the unit cell, a first secondary trace connecting the first primary trace and the second primary trace, and a first tertiary trace branching away from the first secondary trace between the first primary trace and the second primary trace. An area of the first sensor element is greater than an area of the second sensor element within the unit cell.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: September 6, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Cole D. Wilson, Patrick N Prendergast, Jonathan R Peterson
  • Patent number: 9360972
    Abstract: An example apparatus includes a sensing area including a sensor matrix, a first conductor and a second conductor. The first conductor is coupled to a first sensor of the sensor matrix and is configured to be coupled to a sensing module. The second conductor is coupled to a second sensor of the sensor matrix and is configured to be coupled to the sensing module. In embodiments, the first sensor consumes a first area, the second sensor and a length of the first conductor reside within a second area that is smaller than or equal to the first area consumed by the first sensor, and the length of the first conductor is routed between an edge of the sensing area and the second sensor.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 7, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Benjamin James Avery, Cole D. Wilson, Jonathan R. Peterson
  • Publication number: 20150286316
    Abstract: Embodiments described herein provide capacitive sensor arrays. The capacitive sensor arrays include a plurality of column sensor elements arranged in a plurality of columns and a plurality of row sensor elements arranged in a plurality of rows. The plurality of rows and the plurality of columns are arranged such that each of the row sensor elements is at least partially within a gap between adjacent ones of the column sensor elements. A capacitance between a first portion of one of the columns and an adjacent first portion of one of the rows is greater than a capacitance between a second portion of one of the columns and an adjacent second portion of one of the rows.
    Type: Application
    Filed: March 20, 2015
    Publication date: October 8, 2015
    Inventors: Jonathan R. Peterson, Cole D. Wilson
  • Publication number: 20150193052
    Abstract: A system made up of a first device which includes a communication interface and a processing device and a second device which includes a touch sensor assembly and a controller, where the controller uses the touch sensor assembly to communicate with the processing device through a capacitor that is jointly formed by the touch sensor assembly and a conductive portion of the communications interface.
    Type: Application
    Filed: January 29, 2015
    Publication date: July 9, 2015
    Inventors: Thomas Fuller, Cole D. Wilson, Jonathan R. Peterson, David G. Wright
  • Patent number: 8730187
    Abstract: An apparatus includes a memory and a processing device comprising touch sorting logic. The touch sorting logic sorts the raw touch position data in two stages. In each of the stages, the touch sorting logic predicts the centroid positions for each touch of the plurality of touches, compares the predicted centroid positions for each touch and indexes the centroid position for each touch based on the predicted centroid position that is closest to the raw touch position data. The sorted touch position data is sorted according to the touch index assigned to each of the centroid positions for each of the plurality of touches.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: May 20, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Cole D. Wilson, Dana Jon Olson
  • Publication number: 20120044151
    Abstract: A method and apparatus for sorting raw touch position data.
    Type: Application
    Filed: June 2, 2010
    Publication date: February 23, 2012
    Inventors: Cole D. Wilson, Dana Jon Olson