Abstract: A system for, and method of, tracking harvested seafood is provided. The system comprises an origin logging unit for logging the origin of a seafood harvest, a quality grading unit for logging the grade of an individual seafood of the seafood harvest, and a quality control subsystem for monitoring conditions of the seafood harvest during storage. The method comprises logging the origin of a seafood harvest, logging the grade of the seafood harvest, and monitoring the seafood harvest during storage.

Abstract: Systems and methods for positioning horizontal wells within a limited-pre-defined boundary. The systems and methods include an automated process for creating jointed target pairs or horizontal laterals to be utilized for planning horizontal wells in order to position the horizontal laterals within limited pre-defined boundary(ies).

Abstract: A FinFet capacitor structure includes a first, second, third, and fourth FinFet fin, a contiguous gate layer over the fins, first and second source/drain contacts in direct physical contact with the first FinFet fin on either side of the gate layer, a first gate contact in direct physical contact with a portion of the contiguous gate layer directly over the second FinFet fin, third and fourth source/drain contacts in direct physical contact with the third FinFet fin on either side of the gate layer, and a second gate contact in direct physical contact with a portion of the contiguous gate layer directly over the fourth FinFet fin. The first, second, third, and fourth source/drain contacts are all connected to a first power supply rail, and the first and second gate contacts are all connected to a second power supply rail.

Abstract: A scan circuit and methods of operating a scan circuit are provided. The method for operating a scan circuit includes providing a first scan flip-flop which includes an overwrite feature. With the overwrite feature enabled, a change in functional behavior of the first scan flip-flop occurs based on a control signal. The method may further include capturing data at a first input of the first scan flip-flop during a first state of the control signal and resetting captured data by using the overwrite feature during a first transition of the control signal. The method may further include forming a scan chain with one or more of the first scan flip-flops and one or more second scan flip-flops. The second scan flip-flops may include a similar overwrite feature, having the overwrite feature disabled.

Abstract: An integrated circuit includes a plurality of state retention power gating (SRPG) flip-flops coupled in a first chain, wherein the first chain has a first scan input and a first scan output; a pseudo random pattern generator (PRPG) configured to generate test patterns in response to seeds; a multiplexer (MUX) coupled between the PRPG and the first scan input and coupled to receive a select signal; and response compression logic coupled to the first scan output and configured to generate a test signature in response to an output pattern provided at the first scan output. The MUX is configured to, when the select signal has a first value, couple a first output of the PRPG to the first scan input, and, when the select signal has a second value, couple an inversion of the first output of the PRPG to the first scan input.

Abstract: An integrated circuit device includes a peripheral control circuit configured to receive a low power intent signal from a first processor, and a first control register in the peripheral control circuit. The first control register includes a peripheral enable indicator for each processor that can use a first peripheral. Acknowledgement logic circuitry is configured to assert a first low power acknowledgement signal when the first processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the first processor in the first control register.

Abstract: An integrated circuit includes a plurality of state retention power gating (SRPG) flip-flops coupled in a first chain, wherein the first chain has a first scan input and a first scan output; a pseudo random pattern generator (PRPG) configured to generate test patterns in response to seeds; a multiplexer (MUX) coupled between the PRPG and the first scan input and coupled to receive a select signal; and response compression logic coupled to the first scan output and configured to generate a test signature in response to an output pattern provided at the first scan output. The MUX is configured to, when the select signal has a first value, couple a first output of the PRPG to the first scan input, and, when the select signal has a second value, couple an inversion of the first output of the PRPG to the first scan input.

Abstract: An integrated circuit device includes a peripheral control circuit configured to receive a low power intent signal from a first processor, and a first control register in the peripheral control circuit. The first control register includes a peripheral enable indicator for each processor that can use a first peripheral. Acknowledgement logic circuitry is configured to assert a first low power acknowledgement signal when the first processor issuing the low power intent signal has enabled use of the first peripheral as indicated by the peripheral enable indicator for the first processor in the first control register.

Abstract: Systems and methods for positioning horizontal wells within a limited-pre-defined boundary. The systems and methods include an automated process for creating jointed target pairs or horizontal laterals to be utilized for planning horizontal wells in order to position the horizontal laterals within limited pre-defined boundary(ies).

Abstract: Systems and methods for positioning horizontal wells within a limited-pre-defined boundary. The systems and methods include an automated process for creating jointed target pairs or horizontal laterals to be utilized for planning horizontal wells in order to position the horizontal laterals within limited pre-defined boundary(ies).

Abstract: A scan circuit and methods of operating a scan circuit are provided. The method for operating a scan circuit includes providing a first scan flip-flop which includes an overwrite feature. With the overwrite feature enabled, a change in functional behavior of the first scan flip-flop occurs based on a control signal. The method may further include capturing data at a first input of the first scan flip-flop during a first state of the control signal and resetting captured data by using the overwrite feature during a first transition of the control signal. The method my further include forming a scan chain with one or more of the first scan flip-flops and one or more second scan flip-flops. The second scan flip-flops may include a similar overwrite feature, having the overwrite feature disabled.

Abstract: Methods and systems are disclosed for reducing engine flywheel power reduction of an engine while protecting a drivetrain. The method includes monitoring transmission gear selection; determining reduction in flywheel power to protect the drivetrain; and monitoring engine power consumption by other engine power loads. When other engine power loads consume less power than the reduction in flywheel power to protect the drivetrain, the method includes reducing flywheel power by the power difference. When other engine power loads consume the same or more power than the reduction in flywheel power to protect the drivetrain, the method includes not reducing the flywheel power. Engine power can be consumed by both on-vehicle and off-vehicle power loads. Engine power can be consumed by an electric generator and/or a plurality of inverters, and their power consumption can be monitored. Information and commands can be communicated over a controller area network (CAN) bus.

Abstract: Methods and systems are disclosed for reducing engine flywheel power reduction of an engine while protecting a drivetrain. The method includes monitoring transmission gear selection; determining reduction in flywheel power to protect the drivetrain; and monitoring engine power consumption by other engine power loads. When other engine power loads consume less power than the reduction in flywheel power to protect the drivetrain, the method includes reducing flywheel power by the power difference. When other engine power loads consume the same or more power than the reduction in flywheel power to protect the drivetrain, the method includes not reducing the flywheel power. Engine power can be consumed by both on-vehicle and off-vehicle power loads. Engine power can be consumed by an electric generator and/or a plurality of inverters, and their power consumption can be monitored. Information and commands can be communicated over a controller area network (CAN) bus.

Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

Abstract: Systems and methods for positioning horizontal wells within a limited-pre-defined boundary. The systems and methods include an automated process for creating jointed target pairs or horizontal laterals to be utilized for planning horizontal wells in order to position the horizontal laterals within limited pre-defined boundary(ies).

Abstract: Systems and methods for positioning horizontal wells within a limited-pre-defined boundary. The systems and methods include an automated process for creating jointed target pairs or horizontal laterals to be utilized for planning horizontal wells in order to position the horizontal laterals within limited pre-defined boundary(ies).

Abstract: A data processing system includes first and second power distribution networks to provide power at first and second voltages, and a flip-flop. The second voltage is less than the first voltage. The flip-flop includes a master latch with a power node connected to the first power distribution network, a data signal input, and an output signal output that is driven at the first voltage, and a slave latch with a power node connected to the first power distribution network, an input coupled to the output of the master latch, a slave latch output signal output that is driven by the first voltage, and a feedback circuit with a first latch inverter having a power node connected to the second voltage, an input coupled to the master latch output, and an output terminal to provide an output signal that is driven by the second voltage.

Abstract: This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.

Abstract: This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.

Abstract: This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.