Abstract: An embedded processor system having a single-chip embedded microprocessor with analog and digital electrical interfaces to external systems. A novel processor core uses pipelined execution of multiple independent or dependent concurrent threads, together with supervisory control for monitoring and controlling the processor thread state and access to other components. The pipeline enables simultaneous execution of multiple threads by selectively avoiding memory or peripheral access conflicts through the types of pipeline stages chosen and the use of dual and tri-port memory techniques. The single processor core executes one or multiple instruction streams on multiple data streams in various combinations under the control of single or multiple threads.

Abstract: A wireless system for video game control comprised of a base transceiver engaged with an electronic game device where said base transceiver communicates wirelessly with one or more wireless controllers concurrently and which implements a variety of techniques to achieve significant advantages in the areas of latency, reliability, power consumption, and cross platform compatibility.

Abstract: An embedded processor system having a single-chip embedded microprocessor, with analog and digital electrical interfaces to external systems, that is suitable for implementation in various integrated circuit technology formats. A processor core uses pipelined execution of multiple independent or dependent concurrent threads, together with supervisory control for monitoring and controlling the processor thread state and access to other components. The pipeline enables simultaneous execution of multiple threads by selectively avoiding memory or peripheral access conflicts through the types of pipeline stages chosen and the use of dual and tri-port memory techniques. The single processor core executes one or multiple instruction streams on multiple data streams in various combinations under the control of single or multiple threads. The invention can also support a programmable clock mechanism, thread-level monitoring capability, and power management capability.

Abstract: An embedded processor system having a single-chip embedded microprocessor with analog and digital electrical interfaces to external systems. A novel processor core uses pipelined execution of multiple independent or dependent concurrent threads, together with supervisory control for monitoring and controlling the processor thread state and access to other components. The pipeline enables simultaneous execution of multiple threads by selectively avoiding memory or peripheral access conflicts through the types of pipeline stages chosen and the use of dual and tri-port memory techniques. The single processor core executes one or multiple instruction streams on multiple data streams in various combinations under the control of single or multiple threads.

Abstract: A portable game controller for operating an electronic game device. The controller communicates between a person and the game device with a radio frequency sender and receiver. Signal transmission is communicated over the same channel with time domain multiplexing, and can be sent over one or more channels to expand the number of controllers operable in a system. Signal transmission can be delivered in short intervals to conserve battery power. Multiple persons can deliver signals through multiple senders or through a common radio frequency sender, and signals can be transmitted from the radio frequency receiver to the radio frequency sender.