Abstract: A method of fabrication of a superconducting device includes forming a first portion of the superconducting device on a first chip, a second portion of the superconducting device on a second chip, and bonding the first chip to the second chip, arranged in a flip-chip configuration. The first portion of the superconducting device on the first chip includes a dissipative portion of the superconducting device. A multi-layer superconducting integrated circuit is implemented so that noise-susceptible superconducting devices are positioned in wiring layers formed from a low-noise superconductive material and that underlie wiring layers that are formed from a different superconductive material.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: Programmable components of a quantum processor may be selectively programmed using digital to analog converters (DACs). A DAC with a first stage and a second stage and first and second quantum flux parametron (OFF) loops galvanically coupled to and extending from a respective one of the first stage and the second stage is discussed. The first stage has a first storage loop interrupted by a first Josephson junction and an interface for communicating with an external component. The second stage has a second storage loop interrupted by a second Josephson junction, the second storage loop galvanically coupled to the first storage loop, the first Josephson junction and the second Josephson junction coupled in series to a first control line. A method of loading flux quanta into targeted DAC stages is also discussed.

Abstract: A circuit can include a galvanic coupling of a coupler to a qubit by a segment of kinetic inductance material. The circuit can include a galvanic kinetic inductance coupler having multiple windings. The circuit can include a partially-galvanic coupler having multiple windings. The partially-galvanic coupler can include a magnetic coupling and a galvanic coupling. The circuit can include an asymmetric partially-galvanic coupler having a galvanic coupling and a first magnetic coupling to one qubit and a second magnetic coupling to a second qubit. The circuit can include a compact kinetic inductance qubit having a qubit body loop comprising a kinetic inductance material. A multilayer integrated circuit including a kinetic inductance layer can form a galvanic kinetic inductance coupling. A multilayer integrated circuit including a kinetic inductance layer can form at least a portion of a compact kinetic inductance qubit body loop.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: An electrical filter includes a dielectric substrate with inner and outer coils about a first region and inner and outer coils about a second region, a portion of cladding removed from wires that form the coils and coupled to electrically conductive traces on the dielectric substrate via a solder joint in a switching region. An apparatus to thermally couple a superconductive device to a metal carrier with a through-hole includes a first clamp and a vacuum pump. A composite magnetic shield for use at superconductive temperatures includes an inner layer with magnetic permeability of at least 50,000; and an outer layer with magnetic saturation field greater than 1.2 T, separated from the inner layer by an intermediate layer of dielectric. An apparatus to dissipate heat from a superconducting processor includes a metal carrier with a recess, a post that extends upwards from a base of the recess and a layer of adhesive on top of the post. Various cryogenic refrigeration systems are described.

Abstract: Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

Abstract: An electrical filter includes a dielectric substrate with inner and outer coils about a first region and inner and outer coils about a second region, a portion of cladding removed from wires that form the coils and coupled to electrically conductive traces on the dielectric substrate via a solder joint in a switching region. An apparatus to thermally couple a superconductive device to a metal carrier with a through-hole includes a first clamp and a vacuum pump. A composite magnetic shield for use at superconductive temperatures includes an inner layer with magnetic permeability of at least 50,000; and an outer layer with magnetic saturation field greater than 1.2 T, separated from the inner layer by an intermediate layer of dielectric. An apparatus to dissipate heat from a superconducting processor includes a metal carrier with a recess, a post that extends upwards from a base of the recess and a layer of adhesive on top of the post. Various cryogenic refrigeration systems are described.