Abstract: A semiconductor device comprises a plurality of transistor mismatch circuits formed on a semiconductor wafer; and a characterization circuit formed on the semiconductor wafer. The characterization circuit is coupled to receive input provided by the absolute value circuits simultaneously which themselves receive inputs from the mismatch circuits simultaneously and is configured to output a standard deviation of mismatch between transistors in the mismatch circuits.

Abstract: A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor.

Abstract: A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor.

Abstract: A semiconductor device comprises a plurality of transistor mismatch circuits formed on a semiconductor wafer; and a characterization circuit formed on the semiconductor wafer. The characterization circuit is coupled to receive input provided by the absolute value circuits simultaneously which themselves receive inputs from the mismatch circuits simultaneously and is configured to output a standard deviation of mismatch between transistors in the mismatch circuits.

Abstract: A method for evaluating component mismatch in a circuit includes performing a nominal circuit simulation, selecting a set of matched devices, each matched device having at least one process parameter associated therewith, altering a process parameter by one standard deviation, executing an altered circuit simulation, determining a deviation from a nominal value of at least one circuit performance measure, and repeating the altering, executing and determining steps for each process parameter of each matched device. A mismatch evaluation tool includes a computer, a user interface coupled to the computer, and a program storage device coupled to the computer, and embodying a mismatch evaluator.