Patents by Inventor Colin Carver
Colin Carver has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088701Abstract: A constant voltage may be used during battery charging to reduce or avoid the formation of a dendrite, such as a stepped constant voltage. For each charging period, each level of the stepped constant voltage may be calculated to ensure a corresponding current level within each period remains below a safe current limit. A voltage transition between any two periods may occur in response to expiration of a predetermined time, or in response to a determination that the current level has fallen below a lower current limit. A current level during each period may be maintained such that the battery heat is maintained below a reference heat level, which may increase battery cycle life (e.g., battery capacity or maximum recharging cycles). The battery heat may be measured directly or indirectly, or may be estimated based on other measured or controlled values.Type: ApplicationFiled: September 12, 2022Publication date: March 14, 2024Inventors: Naoki Matsumura, Colin Carver, Tod Schiff
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Patent number: 11887887Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.Type: GrantFiled: June 27, 2022Date of Patent: January 30, 2024Assignee: Intel CorporationInventors: Manish Chandhok, Ramanan Chebiam, Brennen Mueller, Colin Carver, Jeffery Bielefeld, Nafees Kabir, Richard Vreeland, William Brezinski
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Patent number: 11784123Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.Type: GrantFiled: February 22, 2022Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Richard Vreeland, Colin Carver, William Brezinski, Michael Christenson, Nafees Kabir
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Publication number: 20220336267Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.Type: ApplicationFiled: June 27, 2022Publication date: October 20, 2022Applicant: Intel CorporationInventors: Manish Chandhok, Ramanan Chebiam, Brennen Mueller, Colin Carver, Jeffery Bielefeld, Nafees Kabir, Richard Vreeland, William Brezinski
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Patent number: 11404307Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.Type: GrantFiled: September 27, 2019Date of Patent: August 2, 2022Assignee: Intel CorporationInventors: Manish Chandhok, Ramanan Chebiam, Brennen Mueller, Colin Carver, Jeffery Bielefeld, Nafees Kabir, Richard Vreeland, William Brezinski
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Publication number: 20220181251Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Applicant: Intel CorporationInventors: Richard Vreeland, Colin Carver, William Brezinski, Michael Christenson, Nafees Kabir
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Patent number: 11289421Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.Type: GrantFiled: September 26, 2019Date of Patent: March 29, 2022Assignee: Intel CorporationInventors: Richard Vreeland, Colin Carver, William Brezinski, Michael Christenson, Nafees Kabir
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Publication number: 20210098360Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Applicant: Intel CorporationInventors: Manish Chandhok, Ramanan Chebiam, Brennen Mueller, Colin Carver, Jeffery Bielefeld, Nafees Kabir, Richard Vreeland, William Brezinski
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Publication number: 20210098359Abstract: Composite integrated circuit (IC) device structures that include two components coupled through hybrid bonded interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over a substantially planar dielectric and metallization layer. A surface of a metallization feature may be augmented with supplemental metal, for example to at least partially backfill a recess in a surface of the metallization feature as left by a planarization process. In some exemplary embodiments, supplemental metal is deposited selectively onto a metallization feature through an autocatalytic (electroless) metal deposition process. A surface of a dielectric material surrounding a metallization feature may also be recessed, for example to at least partially neutralize a recess in an adjacent metallization feature, for example resulting from a planarization process.Type: ApplicationFiled: September 26, 2019Publication date: April 1, 2021Applicant: Intel CorporationInventors: Richard Vreeland, Colin Carver, William Brezinski, Michael Christenson, Nafees Kabir