Patents by Inventor Colin Eddy
Colin Eddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11620220Abstract: A cache memory system including a primary cache and an overflow cache that are searched together using a search address. The overflow cache operates as an eviction array for the primary cache. The primary cache is addressed using bits of the search address, and the overflow cache is addressed by a hash index generated by a hash function applied to bits of the search address. The hash function operates to distribute victims evicted from the primary cache to different sets of the overflow cache to improve overall cache utilization. A hash generator may be included to perform the hash function. A hash table may be included to store hash indexes of valid entries in the primary cache. The cache memory system may be used to implement a translation lookaside buffer for a microprocessor.Type: GrantFiled: December 12, 2014Date of Patent: April 4, 2023Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Colin Eddy, Rodney E. Hooker
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Patent number: 11467972Abstract: In one embodiment, a microprocessor, comprising: a first data cache; and a second data cache configured to process both a miss in the first data cache resulting from a first load or store operation and an eviction from the first data cache to accommodate the first load or store operation, the second data cache configured to indicate to the first data cache that the eviction is complete before the eviction is actually complete based on a first state corresponding to the eviction.Type: GrantFiled: December 1, 2020Date of Patent: October 11, 2022Assignee: CENTAUR TECHNOLOGY, INC.Inventors: Douglas Raye Reed, Colin Eddy
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Publication number: 20220171712Abstract: In one embodiment, a microprocessor, comprising: a first data cache; and a second data cache configured to process both a miss in the first data cache resulting from a first load or store operation and an eviction from the first data cache to accommodate the first load or store operation, the second data cache configured to indicate to the first data cache that the eviction is complete before the eviction is actually complete based on a first state corresponding to the eviction.Type: ApplicationFiled: December 1, 2020Publication date: June 2, 2022Inventors: Douglas Raye Reed, Colin Eddy
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Patent number: 11314657Abstract: In one embodiment, a microprocessor, comprising: a translation lookaside buffer (TLB) configured to indicate that a virtual page address corresponding to a physical page address of a page of memory that a memory access instruction is attempting to access is missing in the TLB; a first micro-op corresponding to a first memory access instruction and configured to initiate a first speculative tablewalk based on a miss in the TLB of a first virtual page address; and a second micro-op corresponding to a second memory access instruction, the second micro-op configured to take over an active first speculative tablewalk of the first micro-op at its current stage of processing based on being older than the first micro-op and further based on having a virtual page address and properties that match the first virtual page address and properties for the first memory access instruction.Type: GrantFiled: December 2, 2020Date of Patent: April 26, 2022Assignee: CENTAUR TECHNOLOGY, INC.Inventor: Colin Eddy
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Patent number: 10387318Abstract: A processor includes a prefetcher that prefetches data in response to memory accesses, wherein each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. The processor also includes a table that holds scores that indicate effectiveness of the prefetcher to prefetch data with respect to the plurality of predetermined MATs. The prefetcher prefetches data in response to memory accesses at a level of aggressiveness based on the scores held in the table and the associated MATs of the memory accesses.Type: GrantFiled: December 14, 2014Date of Patent: August 20, 2019Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTDInventors: Rodney E. Hooker, Douglas R. Reed, John Michael Greer, Colin Eddy
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Patent number: 10228944Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.Type: GrantFiled: November 24, 2015Date of Patent: March 12, 2019Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10209996Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.Type: GrantFiled: December 14, 2014Date of Patent: February 19, 2019Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10175984Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.Type: GrantFiled: November 24, 2015Date of Patent: January 8, 2019Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTDInventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10146547Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.Type: GrantFiled: December 14, 2014Date of Patent: December 4, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10146540Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.Type: GrantFiled: November 24, 2015Date of Patent: December 4, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTDInventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10146546Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an advanced programmable interrupt controller (APIC), configured to perform interrupt operations.Type: GrantFiled: December 14, 2014Date of Patent: December 4, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTDInventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10146539Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an advanced programmable interrupt controller (APIC), configured to perform interrupt operations.Type: GrantFiled: November 24, 2015Date of Patent: December 4, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10133579Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include system memory, coupled an out-of-order processor via a memory bus.Type: GrantFiled: December 14, 2014Date of Patent: November 20, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10133580Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.Type: GrantFiled: December 14, 2014Date of Patent: November 20, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTDInventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10127046Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include system memory, coupled an out-of-order processor via a memory bus.Type: GrantFiled: November 24, 2015Date of Patent: November 13, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10120689Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a control element, coupled to the out-of order processor via a control bus.Type: GrantFiled: November 24, 2015Date of Patent: November 6, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTDInventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10114794Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.Type: GrantFiled: December 14, 2014Date of Patent: October 30, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTDInventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10114646Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.Type: GrantFiled: November 24, 2015Date of Patent: October 30, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTDInventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10108428Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory, where the specified load instruction requires more than a first number of clock cycles to retrieve the operand. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.Type: GrantFiled: December 14, 2014Date of Patent: October 23, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTDInventors: Gerard M. Col, Colin Eddy, G. Glenn Henry
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Patent number: 10108430Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a control element, coupled to the out-of order processor via a control bus.Type: GrantFiled: December 14, 2014Date of Patent: October 23, 2018Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTDInventors: Gerard M. Col, Colin Eddy, G. Glenn Henry