Abstract: A method of testing a capacitive transducer circuit, for example a MEMS capacitive transducer, by applying a test signal via one or more capacitors provided in the transducer circuit.

Abstract: A method of testing a capacitive transducer circuit, for example a MEMS capacitive transducer, by applying a test signal via one or more capacitors provided in the transducer circuit.

Abstract: A method of testing a capacitive transducer circuit, for example a MEMS capacitive transducer, by applying a test signal via one or more capacitors provided in the transducer circuit.

Abstract: A capacitive transducer circuit comprises a capacitive transducer having first and second electrodes. The first and second electrodes are biased by respective first and second bias voltages. An amplifier is connected to receive a first analog signal on an input terminal, the first analog signal being generated by the capacitive transducer, and to generate a second analog signal on an output terminal. A digital feedback circuit is connected between the output terminal of the amplifier and the input terminal of the amplifier. The digital feedback circuit is configured to provide one of said first or second bias voltages. The output of a voltage source which provides the other bias voltage for the capacitive transducer may be filtered by a low pass filter. The low pass filter may comprise a switched capacitor filter circuit.

Abstract: A method of testing a capacitive transducer circuit, for example a MEMS capacitive transducer, by applying a test signal via one or more capacitors provided in the transducer circuit.

Abstract: An apparatus comprising a capacitive transducer, for example a MEMS microphone. A first voltage generator is connected to receive a first voltage (VDD*) and generate a second voltage (VCP) for biasing the capacitive transducer. A control circuit is adapted to, in use, control the first voltage (VDD*) based on a calibration value, wherein a different calibration value would lead to a different first voltage level and the calibration value is set such that an input signal of known amplitude produces an output signal of predetermined amplitude.

Abstract: A method of testing a capacitive transducer circuit, for example a MEMS capacitive transducer, by applying a test signal via one or more capacitors provided in the transducer circuit.

Abstract: A capacitive transducer circuit comprises a capacitive transducer having first and second electrodes. The first and second electrodes are biased by respective first and second bias voltages. An amplifier is connected to receive a first analogue signal on an input terminal, the first analogue signal being generated by the capacitive transducer, and to generate a second analogue signal on an output terminal. A digital feedback circuit is connected between the output terminal of the amplifier and the input terminal of the amplifier. The digital feedback circuit is configured to provide one of said first or second bias voltages. The output of a voltage source which provides the other bias voltage for the capacitive transducer may be filtered by a low pass filter. The low pass filter may comprise a switched capacitor filter circuit.

Abstract: A method of testing a capacitive transducer circuit, for example a MEMS capacitive transducer, by applying a test signal via one or more capacitors provided in the transducer circuit.

Abstract: An apparatus comprising a capacitive transducer, for example a MEMS microphone. A first voltage generator is connected to receive a first voltage (VDD*) and generate a second voltage (VCP) for biasing the capacitive transducer. A control circuit is adapted to, in use, control the first voltage (VDD*) based on a calibration value, wherein a different calibration value would lead to a different first voltage level and the calibration value is set such that an input signal of known amplitude produces an output signal of predetermined amplitude.

Abstract: A method and apparatus for applying a test signal to a node of a signal path of an integrated circuit using a parasitic capacitance of the integrated circuit associated with the node. For example, a parasitic capacitance associated with a bond pad may be used to apply a test signal to a signal path. Alternatively, a parasitic capacitance associated with a shielding element may be used to apply a test signal to the signal path.