Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

Abstract: A sigma delta analog-to-digital converter (ADC) circuit comprises a capacitive gain amplifier circuit having a first input to receive an input voltage and a second input; a loop filter circuit connected to an output of the capacitive gain amplifier circuit; a sub-ADC circuit including an output and an input connected to an output of the loop filter circuit; and a digital-to-analog (DAC) circuit including a DAC input connected to the output of the sub-ADC circuit, and a DAC output connected to the second input of the capacitive gain amplifier.

Abstract: A blood oxygenation sensor is provided comprising: a first current-powered light source to produce light having a first wavelength; a second current-powered light source to produce light having a second wavelength; a light sensor to produce a current signal having a magnitude that is indicative of intensity of light incident upon it; a current level driver circuit that includes a current source configured to couple the current source to alternatively provide current to one of the first current-powered light source and the second light current-powered light source; a processor configured to predict times of occurrence of one or more first time intervals in which arterial volume at a tissue site is at one of a maximum and a minimum; wherein the processor is configured to control the current source, to provide a first pattern of higher power-dissipation current pulses to the first and second current-powered light sources during the first time intervals, and to provide a second pattern of lower power-dissipation

Abstract: Various examples are directed to configuring a configurable hardware module to perform a measurement of a physical quantity. A configuration manager may receive an indication of the physical quantity and performance factor data describing the measurement of the physical quantity. The configuration manager may generate a hardware configuration of the hardware based at least in part on the indication of the physical quantity and the performance factor data. The hardware configuration may comprise instruction data to configure the hardware module to execute a dynamic measurement of the physical quantity. The configuration manager may also generate configuration data describing the hardware configuration, wherein the configuration data comprises simulation data comprising input parameters for a simulation of the hardware configuration and hardware configuration data for configuring a hardware module to implement at least a portion of the hardware configuration.

Abstract: A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

Abstract: A control circuit for use with a four terminal sensor, the sensor having first and second drive terminals and first and second measurement terminals, the control circuit arranged to drive at least one of the first and second drive terminals with an excitation signal, to sense a voltage difference between the first and second measurement terminals, and control the excitation signal such that the voltage difference between the first and second measurement terminals is within a target range of voltages, and wherein the control circuit includes N poles in its transfer characteristic and N?1 zeros in its transfer characteristic such that when a loop gain falls to unity the phase shift around a closed loop is not substantially 2? radians or a multiple thereof, where N is greater than 1.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: A control circuit for use with a four terminal sensor, such as a glucose sensor. The Glucose sensor is a volume product and typically its manufacture will want to make it as inexpensively as possible. This may give rise to variable impedances surrounding the active cell of the sensor. Typically the sensor has first and second drive terminals and first and second measurement terminals, so as to help overcome the impedance problem. The control circuit is arranged to drive at least one of the first and second drive terminals with an excitation signal, and control the excitation signal such that a voltage difference between the first and second measurement terminals is within a target range of voltages. To allow the control circuit to work with a variety of measurement cell types the control circuit further comprises voltage level shifters for adjusting a voltage at one or both of the drive terminals, or for adjusting a voltage received from one or both of the measurement terminals.

Abstract: Physical layouts of ratioed circuit elements, such as transistors, are disclosed. Such layouts can maintain electrical characteristics of the ratioed circuit elements relative to one another in the presence of mechanical stresses applied to an integrated circuit, such as an integrated circuit encapsulated in plastic. The ratioed circuit elements can include first and second composite circuit elements formed of first and second groups of circuit elements, respectively, arranged around a center point. The first group of circuit elements can be arranged on a grid and the second group of circuit elements can include four circuit elements spaced approximately the same distance from the center point. Each of the circuit elements in the second group can be off the grid in at least one dimension. The first and second groups of circuit elements can be arranged around a perimeter of dummy circuit elements in some embodiments.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: An amplifier, comprising: an input node; an output node; a gain stage having a gain stage inverting input, a gain stage non-inverting input and a gain stage output; a feedback capacitor connected in a signal path between the gain stage output and the gain stage inverting input; a sampling capacitor connected between the input node and the gain stage inverting input, and a controllable impedance in parallel with the feedback capacitor, wherein the controllable impedance is operable to switch between a first impedance state in which it does not affect current flow through the feedback capacitor, and a second impedance state in which it cooperates with the feedback capacitor form a bandwidth limiting circuit.

Abstract: A method and apparatus for automatic resonance detection is disclosed for a motor-driven mechanical system such as a voice coil motor (VCM) in which a resonance detector and driver are provided. The automatic resonance detector is implemented on the same integrated circuit as the driver, and dynamically determines the natural resonant frequency of the VCM driven by the driver. The resonant frequency is determined by measuring the back electromotive force (BEMF) of the VCM, detecting the slope of the BEMF signal, and determining the resonant frequency from the slope of the BEMF signal.

Abstract: Physical layouts of ratioed circuit elements, such as transistors, are disclosed. Such layouts can maintain electrical characteristics of the ratioed circuit elements relative to one another in the presence of mechanical stresses applied to an integrated circuit, such as an integrated circuit encapsulated in plastic. The ratioed circuit elements can include first and second composite circuit elements formed of first and second groups of circuit elements, respectively, arranged around a center point. The first group of circuit elements can be arranged on a grid and the second group of circuit elements can include four circuit elements spaced approximately the same distance from the center point. Each of the circuit elements in the second group can be off the grid in at least one dimension. The first and second groups of circuit elements can be arranged around a perimeter of dummy circuit elements in some embodiments.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.

Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.