Abstract: Described herein are techniques of characterizing electrical characteristics of a battery cell. The techniques employ a battery monitor coupled to a battery to measure voltage of the battery cell when it is in a recovery state after application of a stimulus (e.g., discharging or charging the battery). The measured voltage of the battery cell in the recovery state is then used to generate a characterization of the battery cell. The characterization may be used, for example, to match the battery cell with one or more similar battery cells to be coupled in a battery pack. In another example, the characterization may be used to verify authenticity of the battery cell.

Abstract: A method of estimating a change of a variable over a measurement window, including the steps of taking multiple samples of the variable during the measurement window, defining a weight to be associated with each sample, the weight varying as a function of position of the sample within the measurement window, processing the samples taking account of their weight to form an estimate of the change in the variable.

Abstract: A signal conditioning circuit for a latching comparator comprising first and second transistors arranged in a long tail pair, the long tail pair having an active load and configured to act as an integrator.

Abstract: A single chip integrated circuit measuring circuit (1) for determining a characteristic of the impedance of an external complex impedance circuit (2) for facilitating characterization of the impedance of the complex impedance circuit (2) comprises a signal generating circuit (7) for generating a variable frequency stimulus signal for applying to the complex impedance circuit (2). A first receiving circuit (10) receives a response signal from the complex impedance circuit (2) in response to the stimulus signal and conditions the response signal. A first analog-to-digital converter (68) converts the conditioned response signal to a first digital output signal, which is read from the first analog-to-digital converter (68) through a first digital output port (14). The response signal from the complex impedance circuit (2) is a current signal, and a current to voltage converter circuit (64) converts the response signal to a voltage signal.

Abstract: The invention provides a thermal sensor having a first and second temperature sensing elements each being formed on a thermally isolated table in a first substrate.

Abstract: A method for one-way coupling an input signal to an integrated circuit on a semiconductor chip with the integrated circuit electrically isolated from the input signal comprises forming a MOS isolation coupler on the semiconductor chip by a CMOS process. The MOS isolation coupler comprises an inductor coil for generating a magnetic field in response to an input signal applied to terminals thereof. A MAGFET having a split drain formed by respective drain portions is formed on the semiconductor chip below the inductor coil, so that a current difference is induced between the drain currents in the drain portions which is proportional to the strength of the magnetic field generated by the inductor coil resulting from the input signal. The MAGFET is formed prior to the inductor coil. An oxide isolating layer is provided over the MAGFET, and the inductor coil is formed on the oxide layer.

Abstract: A signal conditioning circuit for a latching comparator comprising first and second transistors arranged in a long tail pair, the long tail pair having an active load and configured to act as an integrator.

Abstract: The present invention relates to a method and system for reducing integral non linearity errors in a pipeline Analog to Digital Converter (ADC). The invention provides in a first embodiment a method comprising the steps of: adding an analog dither signal to the analog input signal of a pipeline Analog to Digital Converter, and converting the analog input signal to a digital output signal by means of the pipeline Analog to Digital Converter. The amplitude of the analog dither signal is determined by the architecture of the Analog to Digital Converter. The invention also provides in a second embodiment a circuit comprising a pipeline analog to digital converter for converting an analog input signal to a digital output signal and a feedback circuit coupled to the converter such that the digital output signal is adapted to have an average non linearity error value of about zero LSBs.

Abstract: The invention provides a multi-channel DAC circuit which provides for correlation between selected ones of the multiple channels such that a single set of calibration coefficients may be used for calibration of multiple channels.

Abstract: A MOS isolation coupler is formed on a semiconductor chip by a CMOS process and comprises an inductor coil for generating a magnetic field in response to an input signal applied to terminals thereof. A MAGFET having a split drain formed by respective drain portions is formed on the semiconductor chip below the inductor coil, so that a current difference is induced between the drain currents in the drain portions which is proportional to the strength of the magnetic field generated by the inductor coil resulting from the input signal. The MAGFET is formed prior to the inductor coil. An oxide isolating layer is provided over the MAGFET, and the inductor coil is formed on the oxide layer.

Abstract: The invention provides a multi-channel DAC circuit which provides for correlation between selected ones of the multiple channels such that a single set of calibration coefficients may be used for calibration of multiple channels.

Abstract: An analog to digital converter is provided comprising an array of capacitors for sampling an input, each capacitor having at least one associated switch for controllably connecting a terminal of the capacitor to a first reference voltage or to a second reference voltage; and a sequence generator for generating a sequence of bits, wherein during sampling of the input onto the array of capacitors an output of the sequence generator is supplied to the switches of a first group of capacitors to control whether a given capacitor within the first group is connected by its associated switch to the first reference voltage or to the second reference voltage.

Abstract: A analog to digital converter, comprising: an input for receiving an input signal to be digitized; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first residue as a difference between the input signal and the first digital result; a second converter core for performing a second part of the analog to digital conversion by converting the first residue; wherein at least one of the first and second converter cores comprises at least three analog to digital conversion engines and a controller for controlling the operation of the engines such that the engines collaborate to perform a successive approximation search, and wherein a plurality of bits can be determined during a single trial step of the successive approximation search.