Abstract: An accurate, low noise conditionally resetting integrator circuit in an analog to digital system samples, with an analog to digital converter, the output of an integrating circuit a number of times during a measuring period; isolates the input for the integrating circuit during sample event; generates a reset signal in response to the integrating circuit output reaching a predetermined level; and resets the feedback capacitor of the integrating circuit by isolating it from the amplifier circuit of the integrating circuit and connecting it to a reference source during a sample event.

Abstract: A analog to digital converter, comprising: an input for receiving an input signal to be digitised; a first converter core for performing a first part of an analog to digital conversion, and for outputting a first digital result; a first residue calculator for calculating a first residue as a difference between the input signal and the first digital result; a second converter core for performing a second part of the analog to digital conversion by converting the first residue; wherein at least one of the first and second converter cores comprises at least three analog to digital conversion engines and a controller for controlling the operation of the engines such that the engines collaborate to perform a successive approximation search, and wherein a plurality of bits can be determined during a single trial step of the successive approximation search.

Abstract: A DAC (1) has a switched element capacitor (7, Cr) to which charge is delivered via switches (6, S1/S2) depending on required analog voltage level (Vref1, Vref2). An output switch (S3) is closed and a ground switch (S4) is opened to deliver charge to the output according to received bi-level digital inputs (+1, ?1). The control block (2) has a memory and determines an inactive output level if there is an input digital transition from +1 to ?1 or from ?1 to +1. For the inactive level S3 is kept open and S4 is kept closed. Thus, for every clock cycle with one of these transitions there is no charge transfer and hence no thermal noise. Overall noise is therefore considerably reduced.

Abstract: An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.

Abstract: A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch.

Abstract: A sigma-delta digital-to-analog converter comprises a current digital-to-analog converter (IDAC) stage which generates a current depending on an input digital signal. An output current-to-voltage converter converts the generated signal to a voltage on a continuous-time basis. The amplifier used in the output current-to-voltage converter is chopper-stabilized. The converter can be single bit or multi-bit. The IDAC stage can be implemented with a pair of branches, a first branch comprising a first biasing current source and a second branch comprising a second biasing current source. The biasing current sources can be chopper-stabilized by connecting the bias current sources to the output current-to-voltage converter by a set of switches. The switches connect the biasing current sources to the output current-to-voltage converter in a first configuration and a second, reversed, configuration. This modulates flicker noise contributed by the bias current sources to the chopping frequency.

Abstract: The present invention relates to a method and system for reducing integral non linearity errors in a pipeline Analog to Digital Converter (ADC). The invention provides in a first embodiment a method comprising the steps of: adding an analog dither signal to the analog input signal of a pipeline Analog to Digital Converter, and converting the analog input signal to a digital output signal by means of the pipeline Analog to Digital Converter. The amplitude of the analog dither signal is determined by the architecture of the Analog to Digital Converter. The invention also provides in a second embodiment a circuit comprising a pipeline analog to digital converter for converting an analog input signal to a digital output signal and a feedback circuit coupled to the converter such that the digital output signal is adapted to have an average non linearity error value of about zero LSBs.

Abstract: A DAC architecture is described. The architecture is specifically adapted to provided an analog voltage output based on a digital input word. The architecture includes a resistor ladder configuration sub-divisible into a first component, adapted to convert a lower part of the input word, and a second component adapted to convert an upper part of the input word. The DAC is calibrated such that the first component can be used to tune the output of the second component on selection of specific segment from the second component.

Abstract: A gain compensation technique for a fractional-N phase lock loop includes locking a reference signal with the N divider feedback signal in a phase lock loop including a phase detector, charge pump, loop filter and voltage control oscillator with an N divider in its feedback loop; driving the N divider with a sigma delta modulator including at least one integrator to obtain a predetermined fractional-N feedback signal; and commanding a scaling in phase lock loop gain by a predetermined factor and synchronously inversely scaling by that factor the contents of at least one of the integrators.

Abstract: A DAC (1) has a switched element capacitor (7, Cr) to which charge is delivered via switches (6, S1/S2) depending on required analog voltage level (Vref1, Vref2). An output switch (S3) is closed and a ground switch (S4) is opened to deliver charge to the output according to received bi-level digital inputs (+1, ?1). The control block (2) has a memory and determines an inactive output level if there is an input digital transition from +1 to ?1 or from ?1 to +1. For the inactive level S3 is kept open and S4 is kept closed. Thus, for every clock cycle with one of these transitions there is no charge transfer and hence no thermal noise. Overall noise is therefore considerably reduced.

Abstract: A charge pump system for a fast locking phase lock loop includes a set n of charge pump units; and a control logic circuit for enabling the set of n charge pump units to produce up and down charge pulses with a nominal charge pump mismatch in a wide bandwidth mode; and in a narrow bandwidth mode enabling at least a subset of the n charge pump units sequentially to produce an average charge pump mismatch in narrow bandwidth mode that matches the nominal charge pump mismatch in the wide bandwidth mode.

Abstract: A charge pump system for a fast locking phase lock loop includes a set n of charge pump units; and a control logic circuit for enabling the set of n charge pump units to produce up and down charge pulses with a nominal charge pump mismatch in a wide bandwidth mode; and in a narrow bandwidth mode enabling at least a subset of the n charge pump units sequentially to produce an average charge pump mismatch in narrow bandwidth mode that matches the nominal charge pump mismatch in the wide bandwidth mode.

Abstract: A gain compensation technique for a fractional-N phase lock loop includes locking a reference signal with the N divider feedback signal in a phase lock loop including a phase detector, charge pump, loop filter and voltage control oscillator with an N divider in its feedback loop; driving the N divider with a sigma delta modulator including at least one integrator to obtain a predetermined fractional-N feedback signal; and commanding a scaling in phase lock loop gain by a predetermined factor and synchronously inversely scaling by that factor the contents of at least one of the integrators.

Abstract: A fractional-N synthesizer and method of phase synchronizing the output signal with the input reference signal in a fractional-N synthesizer by generating a synchronization pulse at integer multiples of periods of the input reference signal and gating the synchronization pulse to re-initialize the interpolator in the fractional-N synthesizer to synchronize the phase of the output signal with the input reference signal.

Abstract: An analog to digital converter for converting an analog input signal to a digital output signal, includes a first converter having a filter unit for producing at least one filter output signal by filtering the difference between the analog input signal and a feedback signal generated from a first digital output, a quantizer for producing the first digital output by quantizing the weighted sum of a first filter output from the filter unit and the analog input signal, a second converter for producing a second digital output by converting a second filter output from the filter unit, and a digital combiner for combining the first output digital signal and the second output digital signal into the digital output signal.

Abstract: A fractional-N synthesizer and method of phase synchronising the output signal with the input reference signal in a fractional-N synthesizer by generating a synchronisation pulse at integer multiples of periods of the input reference signal and gating the synchronisation pulse to re-initialize the interpolator in the fractional-N synthesizer to synchronize the phase of the output signal with the input reference signal.

Abstract: Sigma delta modulators and pipelined (also called subranging) converters are used widely in Analog to Digital converters. In general pipelined converters are preferred where the highest speed of conversion is required and sigma delta converters are preferred for lower speed where a significant level of oversampling is possible. The present application describes a converter having the advantages of both types of converter.

Abstract: Digital to Analog convertors (DAC's) are prone to mismatch noise, particularly in DAC structures using unequally weighted segments. A digital to analog converter, for use in a data conversion system, for converting a digital input to analog output and having features for reducing mismatch noise comprises a plurality of selectable segments, at least two of which have a first weighting factor and at least two of which have a second weighting factor. The segments when selected are connected to a reference signal, with the output for each segment, when selected, being proportional to the weighting factor of the segments. Selection means select segments based on the digital input. Summing means add the output from each selected segment to produce an analog output. The number of segments having the second weighting factor is equal to at least twice the ratio of the first and second weighting factors less one.

Abstract: In a Sigma Delta converter, a succession of input signal samples are processed in an iterative manner to provide a succession of output signals and feedback signals, which are matched to the input signal samples over a specified frequency range. Two or more successive iterations are carried out in parallel so as to provide a sequence of independent outputs available in parallel. This provision of parallel outputs facilitates an overall increase in the speed of operation of the converter, which is otherwise limited by the maximum available rate of clocking of the converter's filters.

Abstract: Mismatch errors within oversampled analog to digital (ADC) and digital to analog (DAC) data converters limit the overall conversion accuracy. A circuit is provided which interchanges the analog segments within a multibit oversampled converter in a fashion to move the mismatch errors away from the overall converter's passband frequencies and towards other frequencies where they do not interfere with the signal to be converted. The circuit works by minimizing the differences in the signals which control the individual segments. Circuits may be provided for achieving first, second and higher order "shaping" of the mismatch errors. The invention also provides a circuit in which exchange of the analog elements with the DACs of multibit oversampled converters is effected using a circular queue, so moving the mismatch errors to high frequency where they do not interfere with the signal to be converted.