Patents by Inventor Colin McKellar

Colin McKellar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and Systems for Measuring the Security of an Electronic Device Comprising Hardware and Software
    Publication number: 20220405399
    Abstract: A method of assessing the security of an electronic device comprising software and hardware.
    Type: Application
    Filed: May 31, 2022
    Publication date: December 22, 2022
    Inventor: Colin McKellar
  • Deadlock detection in hardware design using assertion based verification
    Patent number: 10083262
    Abstract: Methods and systems for detecting deadlock in a hardware design. The method comprises identifying one or more control signals in the hardware design; generating a state machine for each of the one or more control signals to track the state of the control signal; generating one or more assertions for each control signal to detect that the control signal is in a deadlock state from the state machine; and detecting whether any of the one or more control signal are in a deadlock state using the assertions. The method may also comprise generating one or more fairness constraints to impose on a particular assertion and detecting the particular control signal is in the deadlock state using the assertions under the fairness constraints.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: September 25, 2018
    Assignee: Imagination Technologies Limited
    Inventors: Ashish Darbari, Colin McKellar
  • DEADLOCK DETECTION IN HARDWARE DESIGN USING ASSERTION BASED VERIFICATION
    Publication number: 20170357742
    Abstract: Methods and systems for detecting deadlock in a hardware design. The method comprises identifying one or more control signals in the hardware design; generating a state machine for each of the one or more control signals to track the state of the control signal; generating one or more assertions for each control signal to detect that the control signal is in a deadlock state from the state machine; and detecting whether any of the one or more control signal are in a deadlock state using the assertions. The method may also comprise generating one or more fairness constraints to impose on a particular assertion and detecting the particular control signal is in the deadlock state using the assertions under the fairness constraints.
    Type: Application
    Filed: August 29, 2017
    Publication date: December 14, 2017
    Inventors: Ashish Darbari, Colin McKellar
  • Deadlock detection in hardware design using assertion based verification
    Patent number: 9767236
    Abstract: Methods and systems for detecting deadlock in a hardware design. The method comprises identifying one or more control signals in the hardware design; generating a state machine for each of the one or more control signals to track the state of the control signal; generating one or more assertions for each control signal to detect that the control signal is in a deadlock state from the state machine; and detecting whether any of the one or more control signal are in a deadlock state using the assertions. The method may also comprise generating one or more fairness constraints to impose on a particular assertion and detecting the particular control signal is in the deadlock state using the assertions under the fairness constraints.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: September 19, 2017
    Assignee: Imagination Technologies Limited
    Inventors: Ashish Darbari, Colin McKellar
  • DEADLOCK DETECTION IN HARDWARE DESIGN USING ASSERTION BASED VERIFICATION
    Publication number: 20170177753
    Abstract: Methods and systems for detecting deadlock in a hardware design. The method comprises identifying one or more control signals in the hardware design; generating a state machine for each of the one or more control signals to track the state of the control signal; generating one or more assertions for each control signal to detect that the control signal is in a deadlock state from the state machine; and detecting whether any of the one or more control signal are in a deadlock state using the assertions. The method may also comprise generating one or more fairness constraints to impose on a particular assertion and detecting the particular control signal is in the deadlock state using the assertions under the fairness constraints.
    Type: Application
    Filed: March 31, 2015
    Publication date: June 22, 2017
    Inventors: Ashish Darbari, Colin McKellar
  • DEADLOCK DETECTION IN HARDWARE DESIGN USING ASSERTION BASED VERIFICATION
    Publication number: 20160314223
    Abstract: Methods and systems for detecting deadlock in a hardware design. The method comprises identifying one or more control signals in the hardware design; generating a state machine for each of the one or more control signals to track the state of the control signal; generating one or more assertions for each control signal to detect that the control signal is in a deadlock state from the state machine; and detecting whether any of the one or more control signal are in a deadlock state using the assertions. The method may also comprise generating one or more fairness constraints to impose on a particular assertion and detecting the particular control signal is in the deadlock state using the assertions under the fairness constraints.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 27, 2016
    Inventors: Ashish Darbari, Colin McKellar
  • Texturing 3-dimensional computer graphic images
    Patent number: 8988447
    Abstract: A method and apparatus are provided to generate automatically a mip-map chain of texture images from a portion of texture image data such that it may be used in texturing a computer graphic image. A portion of the texture image data is stored temporarily and is filtered to generate at least one lower level of mip-map data from the texture data. This lower level of mip-map texture image data is then stored for use in texturing. Preferably these are stored on a tile-by-tile basis where a tile is a rectangular area of the image being displayed.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Imagination Technologies, Limited
    Inventor: Colin McKellar
  • TEXTURING 3-DIMENSIONAL COMPUTER GRAPHIC IMAGES
    Publication number: 20140139527
    Abstract: A method and apparatus are provided to generate automatically a mip-map chain of texture images from a portion of texture image data such that it may be used in texturing a computer graphic image. A portion of the texture image data is stored temporarily and is filtered to generate at least one lower level of mip-map data from the texture data. This lower level of mip-map texture image data is then stored for use in texturing. Preferably these are stored on a tile-by-tile basis where a tile is a rectangular area of the image being displayed.
    Type: Application
    Filed: October 14, 2013
    Publication date: May 22, 2014
    Applicant: IMAGINATION TECHNOLOGIES LIMITED
    Inventor: Colin McKellar
  • Texturing 3-dimensional computer graphic images
    Patent number: 8564606
    Abstract: A method and apparatus are provided to generate automatically a mip-map chain of texture images from a portion of texture image data such that it may be used in texturing a computer graphic image. A portion of the texture image data is stored temporarily and is filtered to generate at least one lower level of mip-map data from the texture data. This lower level of mip-map texture image data is then stored for use in texturing. Preferably these are stored on a tile-by-tile basis where a tile is a rectangular area of the image being displayed.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: October 22, 2013
    Assignee: Imagination Technologies, Limited
    Inventor: Colin McKellar
  • Texturing 3-dimensional computer graphic images
    Publication number: 20070052718
    Abstract: A method and apparatus are provided to generate automatically a mip-map chain of texture images from a portion of texture image data such that it may be used in texturing a computer graphic image. A portion of the texture image data is stored temporarily and is filtered to generate at least one lower level of mip-map data from the texture data. This lower level of mip-map texture image data is then stored for use in texturing. Preferably these are stored on a tile-by-tile basis where a tile is a rectangular area of the image being displayed.
    Type: Application
    Filed: June 16, 2004
    Publication date: March 8, 2007
    Inventor: Colin McKellar