Patents by Inventor Colin Perry
Colin Perry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240108939Abstract: A weight training machine comprises: a motor; a line that is tensioned by the motor; a spool that takes up the line, wherein the spool includes a flange wherein the flange defines a capture region for the line; and a line guide adjacent to the spool, wherein the line guide prevents the line from persistently escaping from the capture region for the line.Type: ApplicationFiled: September 11, 2023Publication date: April 4, 2024Inventors: Joseph Perry, David Jonathan Zimmer, Anya Richardson Quenon, David Mallard, Colin Russell Parker
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Patent number: 7672653Abstract: Various embodiments are directed to removing interfering signals in a broadband radio frequency (RF) receiver by implementing a silicon tuner arranged to replicate high quality factor (Q) performance without the advantages of using high Q components available for module tuners. In one or more embodiments, tuned filter elements within a broadband silicon tuner are reused to maximize the attenuation of unwanted signals while minimizing induced undesirable channel ripple. In various implementations, a number of tuned passive inductor/capacitor filter elements are combined as required such that filter elements for an unused frequency band are reconfigured to provide attenuation of and enhanced immunity to unwanted signals. Other embodiments are described and claimed.Type: GrantFiled: March 20, 2007Date of Patent: March 2, 2010Assignee: Intel CorporationInventors: Nick Cowley, Sawyer Albert David, Mark Mudd, Richard Goldman, Colin Perry, Ruiyan Zhao
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Patent number: 7626457Abstract: An Automatic Gain Control (AGC) module for controlling Noise Figure (NF) and IM characteristics therein is disclosed. The AGC module comprises a plurality of AGC stages. Each AGC stage comprises a differential amplifier circuit, an input signal transistor and a current-steering circuit. Differential amplifier circuits of the plurality of AGC stages receive control signals at their differential inputs and their output is connected to a common load. The input signal transistors of the plurality of AGC stages receive a common input signal and is further coupled to the differential amplifier circuit and the current-steering circuit. The current-steering circuits and the control signals at the differential amplifier circuits control gain of the each AGC stage of the plurality of AGC stage, which is used to control the NF and the IM characteristics.Type: GrantFiled: September 28, 2007Date of Patent: December 1, 2009Assignee: Intel CorporationInventors: Mark Mudd, Isaac Ali, Ruiyan Zhao, Nick Cowley, Colin Perry, Richard Goldman
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Publication number: 20090085660Abstract: An Automatic Gain Control (AGC) module for controlling Noise Figure (NF) and IM characteristics therein is disclosed. The AGC module comprises a plurality of AGC stages. Each AGC stage comprises a differential amplifier circuit, an input signal transistor and a current-steering circuit. Differential amplifier circuits of the plurality of AGC stages receive control signals at their differential inputs and their output is connected to a common load. The input signal transistors of the plurality of AGC stages receive a common input signal and is further coupled to the differential amplifier circuit and the current-steering circuit. The current-steering circuits and the control signals at the differential amplifier circuits control gain of the each AGC stage of the plurality of AGC stage, which is used to control the NF and the IM characteristics.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Applicant: INTEL CORPORATIONInventors: Mark Mudd, Isaac Ali, Ruiyan Zhao, Nick Cowley, Colin Perry, Richard Goldman
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Publication number: 20080231759Abstract: Various embodiments are directed to removing interfering signals in a broadband radio frequency (RF) receiver by implementing a silicon tuner arranged to replicate high quality factor (Q) performance without the advantages of using high Q components available for module tuners. In one or more embodiments, tuned filter elements within a broadband silicon tuner are reused to maximize the attenuation of unwanted signals while minimizing induced undesirable channel ripple. In various implementations, a number of tuned passive inductor/capacitor filter elements are combined as required such that filter elements for an unused frequency band are reconfigured to provide attenuation of and enhanced immunity to unwanted signals. Other embodiments are described and claimed.Type: ApplicationFiled: March 20, 2007Publication date: September 25, 2008Inventors: Nick Cowley, Sawyer Albert David, Mark Mudd, Richard Goldman, Colin Perry, Ruiyan Zhao
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Publication number: 20070057744Abstract: A circuit arrangement having a plurality of variable capacitance elements such as varactors is described, the varactors having associated electronic control means which controls the capacitance of the variable capacitance elements over a control range. The control range is such that for any particular variable capacitance element a complete variation from a lowest to a highest capacitance is obtained from only a portion of the control range.Type: ApplicationFiled: October 10, 2006Publication date: March 15, 2007Inventors: Colin Perry, Stephen Parry, Alessandro Deidda, Christopher Shepherd
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Publication number: 20070030087Abstract: A variable capacitance network is disclosed, comprising a plurality of capacitance arms connected in parallel with each other between first and second terminals of the network. Each capacitance arm has a varactor and a series capacitor in series with the varactor A control input applies a common control signal to the junctions between the varactors and their associated series capacitors, to allow for simultaneous control of each varactor.Type: ApplicationFiled: October 10, 2006Publication date: February 8, 2007Inventors: Colin Perry, Stephen Parry, Alessandro Deidda, Christopher Shepherd
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Publication number: 20070030086Abstract: A variable capacitance network is disclosed, comprising a plurality of capacitance arms connected in parallel with each other between first and second terminals of the network. Each capacitance arm has a varactor and a series capacitor in series with the varactor A control input applies a common control signal to the junctions between the varactors and their associated series capacitors, to allow for simultaneous control of each varactor.Type: ApplicationFiled: October 10, 2006Publication date: February 8, 2007Inventors: Colin Perry, Stephen Parry, Alessandro Deidda, Christopher Shepherd
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Patent number: 7102437Abstract: An integrated circuit device includes an amplifier stage comprising a pair of transistors (134A, 134B), the respective bases or gates of which are connected together, as well as the respective emitters or sources. The respective drains or collectors of the transistors are capacitively coupled (166) so as to be effectively shorted at the frequencies of operation of the amplifier, A biasing circuit arrangement (144) is also provided which employs bias control feedback to set the bias currents for the transistors. The biasing circuit arrangement takes as its input the current flowing at one of the electrodes (160) of one of the transistors.Type: GrantFiled: September 9, 2004Date of Patent: September 5, 2006Assignee: Zarlink Semiconductor LimitedInventor: Colin Perry
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Publication number: 20050231283Abstract: An integrated circuit device includes an amplifier stage comprising a pair of transistors (134A, 134B), the respective bases or gates of which are connected together, as well as the respective emitters or sources. The respective drains or collectors of the transistors are capacitively coupled (166) so as to be effectively shorted at the frequencies of operation of the amplifier, A biasing circuit arrangement (144) is also provided which employs bias control feedback to set the bias currents for the transistors. The biasing circuit arrangement takes as its input the current flowing at one of the electrodes (160) of one of the transistors.Type: ApplicationFiled: September 9, 2004Publication date: October 20, 2005Inventor: Colin Perry
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Publication number: 20050134395Abstract: A circuit arrangement having a plurality of variable capacitance elements such as varactors is described, the varactors having associated electronic control means which controls the capacitance of the variable capacitance elements over a control range. The control range is such that for any particular variable capacitance element a complete variation from a lowest to a highest capacitance is obtained from only a portion of the control range.Type: ApplicationFiled: November 16, 2004Publication date: June 23, 2005Inventors: Colin Perry, Stephen Parry, Alessandro Deidda, Christopher Shepherd
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Publication number: 20050128008Abstract: A variable capacitance network is disclosed, comprising a plurality of capacitance arms connected in parallel with each other between first and second terminals of the network. Each capacitance arm has a varactor and a series capacitor in series with the varactor A control input applies a common control signal to the junctions between the varactors and their associated series capacitors, to allow for simultaneous control of each varactor.Type: ApplicationFiled: November 16, 2004Publication date: June 16, 2005Inventors: Colin Perry, Stephen Parry, Alessandro Deidda, Christopher Shepherd