Abstract: A physical unclonable function (PUF) circuit generates one or more bit values. The PUF circuit includes a first one-time programmable (OTP) memory cell, a second OTP memory cell, and a latch circuit connected to the first and second OTP memory cells. The latch circuit initiates programming of the first and second OTP memory cells, detects a faster programming OTP memory cell of the first and second OTP memory cells, inhibits programming of a slower programming OTP memory cell of the first and second OTP memory cells, and stores a first bit value when the first OTP memory cell is the faster programming OTP memory cell and a second bit value when the second OTP memory cell is the faster programming OTP memory cell.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: A protection circuit for an integrated circuit product die or die-let (die-let) is responsive to whether the die-let has undergone a dicing operation or not. A test circuit on the die-let's semiconductor wafer can test and/or configure the die-let. After the dicing operation, the protection circuit generates a signal to isolate the cut input lines from the test circuit to prevent any interference with the normal operation of the integrated circuit product die-let.

Abstract: A low power voltage level shifter circuit in which current is limited through at least one of a plurality of CMOS logic circuits, one of which receives input signals within a first voltage level and is connected between a first upper and lower power supply, a second of which transmits shifted output signals within a second voltage level and is connected between a second upper and lower power supply. There is at least one current-limiting MOS transistor connected between at one of the CMOS logic circuits and one of its power supplies. Typically, there is at least one current-limiting MOS transistor between the second CMOS logic circuit which transmits the shifted output signals which have a larger range than that of the input signals. A second current through the at least one current-limiting MOS transistor mirrors a set current through a first MOS transistor so that power consumed by the CMOS logic circuit during switching is limited.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: A protection circuit for an integrated circuit product die or die-let (die-let) is responsive to whether the die-let has undergone a dicing operation or not. A test circuit on the die-let's semiconductor wafer can test and/or configure the die-let. After the dicing operation, the protection circuit generates a signal to isolate the cut input lines from the test circuit to prevent any interference with the normal operation of the integrated circuit product die-let.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: A low power consuming read circuit for a memory array is disclosed. The circuit is particularly useful in applications where oxide breakdown one-time programmable memory is integrated into a system having low power available from the power sources supplying the system.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: A low power consuming read circuit for a memory array is disclosed. The circuit is particularly useful in applications where oxide breakdown one-time programmable memory is integrated into a system having low power available from the power sources supplying the system.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage.

Abstract: A shift register page buffer for use in an array of multiple bits-per-cell flash EEPROM memory cells so as to render page mode programming and reading is provided. A sensing logic circuit (26,27) is used to selectively and sequentially compare array bit line voltages with each of a plurality of target reference cell bit line voltages. Shift register circuit (300) is responsive to the sensing logic circuit for sequentially storing either a low or high logic level after each comparison of the bit line voltages with one of the plurality of target reference voltages. Each of the shift register circuits is formed of series-connected latch circuits (302-308), each having inputs and outputs. A switching transistor (N5) is interconnected between the sensing logic circuit and the latch circuits and is responsive to a corresponding output of the latch circuits for selectively passing the logic signal from the sensing circuit means to the input of the latch circuits.

Abstract: An improved erasing structure for performing a programming back operation and a concurrent verify operation subsequent to application of an erasing pulse in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and an erase verify reference cell array for generating an upper erased state threshold voltage level. A pre-charge circuit (36a) is used to pre-charge all the array bit lines to a predetermined potential prior to a programming back operation. A reference generator circuit (134) is used for generating a reference output voltage corresponding to a lower erased state threshold voltage level. A switching circuit (P1, N1) is used to selectively disconnect a program current source of approximately 5 .mu.A from the selected certain ones of the columns of array bit lines containing the selected memory core cells which have been correctly programmed back.