Patents by Inventor Colin Stuart

Colin Stuart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063344
    Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and a semi-transparent metallic layer deposited on an LED chip that can dim a light output of the LED chip are disclosed. The thickness of the semi-transparent metal layer can be adjusted based on the desired dimming level. In an embodiment, the metallic layer can be deposited on top of a passivation layer over the LED structure, so that the metallic layer is not electrically coupled to the LED. The metallic layer can additionally cover the mesa sidewalls of the LED structure. The metallic layer can be titanium, or platinum, or other suitable metals in other embodiments. In an embodiment, the metallic layer can be deposited on to the passivation layer, where a length of time the metallic layer is deposited, can be based on the amount of dimming desired.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Inventors: Steven Wuester, Seth Joseph Balkey, Colin Stuart, Peter Andrews
  • Patent number: 11094848
    Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures are disclosed. LED chip structures are disclosed that include reduced bonding topography between active LED structures and carrier submounts. For certain LED chip structures, active LED structures are formed on a growth substrate and subsequently bonded to a carrier substrate. Bonding between active LED structures and carrier submounts is typically provided by metal bonding materials. By providing reduced bonding topography between active LED structures and carrier submounts, bonding strength of metal bonding materials may be improved. Electrical connection configurations for certain layers of active LED structures are disclosed that promote reduced bonding topography. Peripheral border configurations of carrier submounts are also disclosed with that promote reduced bonding topography along the peripheral borders.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: August 17, 2021
    Assignee: CreeLED, Inc.
    Inventors: Luis Breva, Colin Stuart, Michael Check
  • Publication number: 20210050482
    Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures are disclosed. LED chip structures are disclosed that include reduced bonding topography between active LED structures and carrier submounts. For certain LED chip structures, active LED structures are formed on a growth substrate and subsequently bonded to a carrier substrate. Bonding between active LED structures and carrier submounts is typically provided by metal bonding materials. By providing reduced bonding topography between active LED structures and carrier submounts, bonding strength of metal bonding materials may be improved. Electrical connection configurations for certain layers of active LED structures are disclosed that promote reduced bonding topography. Peripheral border configurations of carrier submounts are also disclosed with that promote reduced bonding topography along the peripheral borders.
    Type: Application
    Filed: August 16, 2019
    Publication date: February 18, 2021
    Inventors: Luis Breva, Colin Stuart, Michael Check