Abstract: A non-volatile memory device comprising a volatile memory and a non-volatile memory. The volatile memory comprises a volatile memory circuit, such as a D-type cell, or the like, which incorporates a data input, a volatile storage circuit for storing Q and Q output signals, and Q and Q data outputs. The non-volatile memory comprises circuitry which selectively stores a predetermined one of the Q and Q output signals, and which selectively transfers the stored signal to the volatile memory. The non-volatile memory may comprise, for example, a FATMOS transistor, or the like, and control circuitry coupled thereto. The non-volatile memory also includes transistor circuitry coupled between a voltage source and the FATMOS transistor, for example, which selectively controls the storage and transfer of signals between the non-volatile memory circuit and the volatile storage circuit in conjunction with signals applied to the control circuitry.

Abstract: Memory circuits having a floating gate transistor as a non-volatile storage element are constructed with a shunt transistor across the floating-gate transistor which in the event of a short circuit between the floating gate and the transistor substrate causes the memory to go into a predetermined fail-safe condition. The circuits are cross-coupled flip-flops with a driver and a complementary driver or load connected in series in each of the circuits, one driver or complementary driver or load being a floating gate transistor such as a FATMOS. Short circuiting of the floating gate to the control gate of the floating-gate transistor gives the same fail-safe condition.

Abstract: Non-volatile bistable semiconductor latches having a pair of cross-coupled branches, each branch having a complementary driver or load and a driver connected in series at a respective node; at least one of the complementary drivers or loads, or drivers, includes a non-volatile IGFET having a variable threshold voltage (e.g. a FATMOS), said latch additionally including one or more buffer transistors (e.g. P-channel IGFETS) connected between one or both nodes and a latch output line. The buffer transistors increase the predictability of the state of the latch during power-on in a non-volatile mode of operation. Preferably the complementary drivers or loads, and the drivers, are constructed in CMOS or N-channel MOS. The buffers can drive a single DATA output line of twin DATA, DATA lines in a push-pull configuration.

Abstract: An NMOS non-volatile latch having N-channel drivers Q.sub.1 and Q.sub.2 and variable threshold N-channel FATMOS transistors Q.sub.3 and Q.sub.4 as depletion loads. The control gate of each FATMOS transistor is coupled to its own node (X.sub.1 or X.sub.2) so as to operate in depletion, whereas to obtain the correct voltage stresses the tunnels of the FATMOS floating gates are cross-coupled to the opposite latch nodes.

Abstract: A non-volatile semiconductor latch having at least one variable threshold FATMOS transistor in the cross-coupled latch branches. To accomplish non-volatile reading, the latch nodes (X.sub.1, X.sub.2) are briefly precharged positively so that when the precharging ends and the nodes descend towards the negative supply voltage, the FATMOS(s), by virtue of their varied thresholds, place the latch in its correct logic state dictated by an earlier non-volatile write operation. Precharging, by means of transistors Q.sub.7, Q.sub.8 in parallel with the complementary drivers or loads, and transistors Q.sub.9, Q.sub.10 in series with the drivers in the latch, negates the capacitive effects which can otherwise cause unpredictable non-volatile reading. It also enables non-volatile reading to occur independently from power switch-on--which was necessary with earlier non-volatile FATMOS-containing latches.

Abstract: One disclosed embodiment of the improved digital to analog converters in accordance with the invention comprises means for producing a first series of pulses whose average value is representative of a first group of the bits of an applied digital signal; means for producing a second series of pulses whose average value exceeds that of the first series of pulses by a preselected fixed amount; means for filtering the first and second series of pulses; and means for alternately applying the filtered first or second series of pulses to a smoothing circuit such that the percentage of the time respective ones of said filtered series of pulses are applied to the smoothing circuit is proportional to the value of the remaining bits of the applied digital signal. The output from the smoothing circuit is a direct voltage signal which is representative of the applied digital signal.