Patents by Inventor Colin Weltin-Wu
Colin Weltin-Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072988Abstract: Methods and apparatus for echo cancelation in full duplex communication systems are disclosed. An example method includes generating data for transmission from the first communication device, generating a transmission signal based on the data for transmission, generating an echo cancelation signal based at least in part on the data for transmission and a received signal from a second communication device, and selectively removing a contribution of the received signal to the echo cancelation signal.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Inventors: Ky-Anh Tran, Colin Weltin-Wu
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Patent number: 10158366Abstract: A frequency-to-digital-converter based PLL (FDC-PLL) that implements the functionality of a charge pump and analog-to-digital converter (ADC) with a dual-mode ring oscillator (DMRO) and digital logic. Preferred embodiments of the invention include circuit-level techniques that provide better spurious tone performance and very low phase noise with lower power dissipation and supply voltage than prior digital PLLs known to the inventors.Type: GrantFiled: February 24, 2016Date of Patent: December 18, 2018Assignee: The Regents of the University of CaliforniaInventors: Ian Galton, Colin Weltin-Wu
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Publication number: 20170244544Abstract: A frequency-to-digital-converter based PLL (FDC-PLL) that implements the functionality of a charge pump and analog-to-digital converter (ADC) with a dual-mode ring oscillator (DMRO) and digital logic.Type: ApplicationFiled: February 24, 2016Publication date: August 24, 2017Inventors: Ian Galton, Colin Weltin-Wu
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Patent number: 9184757Abstract: Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.Type: GrantFiled: May 2, 2014Date of Patent: November 10, 2015Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE, THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORKInventors: Mariya Kurchuk, Colin Weltin-Wu, Yannis Tsividis, Dominique Morche, David Lachartre
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Patent number: 8860514Abstract: A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.Type: GrantFiled: December 21, 2012Date of Patent: October 14, 2014Assignee: Silicon Laboratories Inc.Inventors: Colin Weltin-Wu, Yunteng Huang, Manu Seth
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Publication number: 20140241554Abstract: Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.Type: ApplicationFiled: May 2, 2014Publication date: August 28, 2014Applicants: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK, COMMISSARIAT A L'ENERGIE ATOMIQUEInventors: Mariya KURCHUK, Colin WELTIN-WU, Yannis TSIVIDIS, Dominique MORCHE, David LACHARTRE
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Patent number: 8786341Abstract: A digital frequency synthesizer provides absolute phase lock and shorter settling time through the use of a digital filter with a phase and frequency path. Control logic control disables the frequency path during the frequency acquisition and sets a wide bandwidth. After frequency acquisition, a counter with digital phase information is reset using the input clock signal to bring the output phase closer to lock with the input signal and the control logic enables the phase path in the digital loop filter to achieve phase lock with a narrower bandwidth than the initial bandwidth.Type: GrantFiled: March 15, 2013Date of Patent: July 22, 2014Assignee: Silicon Laboratories Inc.Inventors: Colin Weltin-Wu, Yunteng Huang
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Publication number: 20140176201Abstract: A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: SILICON LABORATORIES INC.Inventors: Colin Weltin-Wu, Yunteng Huang, Manu Seth
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Patent number: 8749421Abstract: Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.Type: GrantFiled: October 12, 2010Date of Patent: June 10, 2014Assignees: The Trustees of Columbia University in the City of New York, Commissariat a l'Energie AtomiqueInventors: Mariya Kurchuk, Colin Weltin-Wu, Yannis Tsividis, Dominique Morche, David Lachartre
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Publication number: 20130057423Abstract: Systems, devices, and methods for continuous-time digital signal processing and signal representation are disclosed. This includes a continuous-time analog-to-digital converter that is configured to receive an analog signal and convert it to a continuous-time digital signal without using a clock or any type of sampling. This A/D conversion can include a per-level representation and a per-edge representation of the analog signal to produce a digital signal. The digital signal can then be processed in a continuous-time signal processor. The continuous time signal representation and processing can have benefits such a providing filters in high frequency applications where sampling is not practical.Type: ApplicationFiled: October 12, 2010Publication date: March 7, 2013Applicants: Commissariat A L'Energie Atomique, The Trustees of Columbia University in the City of New YorkInventors: Mariya Kurchuk, Colin Weltin-Wu, Yannis Tsividis, Dominique Morche, David Lachartre
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Patent number: 7940099Abstract: An all-digital phase locked loop (ADPLL) generates a feedback word representing a continuous-time oscillating signal. The ADPLL includes a time-to-digital converter (TDC) configured to be input with the continuous-time oscillating signal and a reference signal. The reference signal is a function of a reference clock signal. The TDC is configured to generate a digital word, the feedback word being a function of the digital word. The ADPLL includes a delay circuit configured to be input with at least one of the reference clock signal and the continuous-time oscillating signal and to be controlled by a first dither signal.Type: GrantFiled: December 3, 2009Date of Patent: May 10, 2011Assignee: STMicroelectronics S.R.L.Inventors: Colin Weltin-Wu, Enrico Stefano Temporiti Milani, Daniele Baldi
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Publication number: 20100141316Abstract: An all-digital phase locked loop (ADPLL) generates a feedback word representing a continuous-time oscillating signal. The ADPLL includes a time-to-digital converter (TDC) configured to be input with the continuous-time oscillating signal and a reference signal. The reference signal is a function of a reference clock signal. The TDC is configured to generate a digital word, the feedback word being a function of the digital word. The ADPLL includes a delay circuit configured to be input with at least one of the reference clock signal and the continuous-time oscillating signal and to be controlled by a first dither signal.Type: ApplicationFiled: December 3, 2009Publication date: June 10, 2010Applicant: STMicroelectronics S.r.I.Inventors: Colin WELTIN-WU, Enrico Stefano Temporiti Milani, Daniele Baldi