Abstract: Methods and apparatus for adjusting the operation of a display device so as to be at least within prescribed form factor or other constraints. In one embodiment of the invention, various operational parameters for a display element are adjusted based on considerations specific to high density form factor constraints. For example, in one such device, a Low Power DisplayPort (LPDP) device having a LPDP source and sink adjust the data rate of the visual data to minimize power consumption while still properly supporting display panel resolutions. In some embodiments, the LPDP source and sink may adjust the transceiver voltages to minimize power consumption. In an alternate embodiment, an LPDP device adjusts data rates to minimize the effects of platform noise. In another aspect of the invention, various display elements of a device coordinate quiescent (“quiet”) mode operation during periods of inactivity.

Abstract: Methods and apparatus for enhanced synchronization of a descrambler, such as used in a signal interface that carries scrambled data. In one embodiment, the descrambler self-synchronizes to a scrambled bit stream (rather than receiving an external “sync” trigger), thereby allowing for much more rapid synchronization. This is accomplished in one variant by identifying a scrambled symbol that has an expected value, predicting an internal scrambler seed based on the expected value, and verifying the predicted seed. For example, an invention-enabled device can synchronize to a DisplayPort stream during blanking intervals which are filled with known “dummy” bytes. Blanking intervals are much more frequent than explicit synchronization symbols, thus an invention enabled device can greatly improve synchronization times, and eliminate e.g., visual artifacts.

Abstract: Methods and apparatus for the selection and/or configuration of scrambling operations to accommodate e.g., both scrambling and non-scrambling connections (such as to e.g., legacy type devices). In one embodiment, media interface devices (such as e.g., HDMI (High-Definition Multimedia Interface)) devices may provide enhanced scrambling capabilities; solutions disclosed herein provide, among other things, support for both enhanced scrambling capable devices and legacy devices, and enable a device to determine the scrambling capabilities of a connected device.

Abstract: An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE 802.3-compliant PHY via a switch; the switch determining whether data transmission is be routed to the IEEE 802.3-compliant PHY or the IEEE 1394-compliant PHY; a first connection, the first connection for transmitting data between a device and the IEEE 802.3-compliant PHY; and a second connection, the second connection for transmitting data between a device and the IEEE 1394-compliant PRY.

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.

Abstract: Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The source processor may be operable to select a frequency from a continuous range of frequencies, and transmit data to the sink processor at the selected frequency. A phase lock circuit may be included in the sink processor. The phase lock circuit may be configured to generate a signal at the selected frequency dependent upon the transmitted data. The generated signal may be in phase with the transmitted data.

Abstract: Methods and apparatus for the intelligent association of control symbols with special symbols that are transmitted over a network. In one embodiment, the association is utilized to improve DC-balance on a transmission medium. In an exemplary variant, the special symbols originate from line codes such as the 8B/10B line code, which format a digital signal so that is optimized for transmission over a given physical channel. These control symbols are divided up according to a first criterion, while the special symbols are further divided up according to a second criterion. The divided control symbols are then allocated to the divided special symbols using a pre-designated allocation algorithm, which may or may not include a scrambling algorithm. The allocation of the control symbols improves signal characteristics and electromagnetic interference (EMI) when various ones of control symbols are ultimately transmitted over a given transmission medium.

Abstract: A system may include a graphics controller and a display. The graphics controller may generate video data to display on the display. The display may include a display panel for displaying the video data, a backlight unit for providing the display panel with backlight, and a display timing controller for communicating with the graphics controller over a communications path. The communications path may include a video data path for conveying video data bits, an interrupt path for conveying interrupts, and a sideband control path for conveying control signals such as a backlight enable signal for the backlight unit. The graphics controller and timing controller may perform link training operations to assess link quality between the graphics controller and timing controller. The timing controller may use interrupts to inform the graphics controller of system status. Use of the interrupts may help the system minimize the time consumed during display power-up operations.

Abstract: Circuits, methods, and apparatus for registers to store information that may be used by devices in a display system. One example provides control and data registers in a display to store information pertaining to a display system that includes the display. The registers can store attributes of the display, a host device, and a branch device. The information may include an organizationally unique identifier, chip identification, major and minor chip revision information, and firmware major and minor revision information.

Abstract: Methods and apparatus for protecting data bus ports and their corresponding PHY devices from taking damage associated with excess voltage across one or more signal pairs during an intermittent connection are provided. Such connections cause the signal pins to carry external device current which raises the signal voltage above the power rails, exceeding the PHY device ratings and causing PHY degradation or destruction. In an exemplary embodiment, an RC circuit is used to detect the voltage level across a signal pair. If this voltage level exceeds a certain preset voltage level, power to the outgoing serial bus port is shut off and return power is abated. While the circuit is responding, the exemplary embodiment uses a 3.6V Zener diode to bleed excess voltage to ground. A current monitor/limiter is also used for limiting current if the voltage level detected exceeds a certain threshold.

Abstract: The present invention provides a method that protects symbol types by characterizing symbols as one of two types—DATA or NON_DATA, generating a symbol characterization bit, placing the symbol characterization bit at both ends of the symbol, and transmitting the symbol with the symbol characterization bits at both ends. Thus, a single byte error may affect a type bit in two consecutive symbols, and will affect one or the other of the type bits in a single symbol, but cannot affect both type bits in a single symbol.

Abstract: An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE 802.3-compliant PHY via a switch; the switch determining whether data transmission is be routed to the IEEE 802.3-compliant PHY or the IEEE 1394-compliant PHY; a first connection, the first connection for transmitting data between a device and the IEEE 802.3-compliant PHY; and a second connection, the second connection for transmitting data between a device and the IEEE 1394-compliant PHY.

Abstract: Methods and apparatus for estimating received error rates. In one embodiment, the estimation of received error rates is conducted in relation to a bus interface such as a high-speed High-Definition Multimedia Interface (HDMI) interface, and the method utilizes corrupted symbols that violate TMDS symbol rules, the corrupted symbols being easily detected and counted. In one exemplary implementation, a symbol error rate (SER) can be estimated from the number of detected invalid symbols. The SER can be used to diagnose the performance of the HDMI interface, and optionally as a basis for selecting or implementing corrective action(s).

Abstract: Methods and apparatus for achieving adaptive de-emphasis on a data network. In one embodiment, the network comprises a high-speed serialized bus network, and the invention is adapted to correct for inter-symbol interference (ISI) associated with data transmissions between two nodes communicating over the network. In one variant, a first device transmits a plurality of symbols to a second device. If the second device detects that these symbols have unacceptably degraded during transmission, it generates an interrupt during a designated interval that is subsequently transmitted to the first device, and used to either attenuate the signal strength associated with data transmissions to the second device, or undertake one or more remedial measures. In another embodiment, sequential calibration of nodes is achieved by executing a process adapted to identify an optimal de-emphasis level associated with data transmissions.

Abstract: A high-speed optical interface for connecting computers to external I/O devices allows a number of native I/O formats to be encapsulated into PCIe Vendor Defined Messages (“VDMs”) for transfer over a single physical medium, preferably optical, and is thus referred to as the converged I/O (“CIO”) interface. Standard PCIe bridges are modified to support peer-to-peer communications, allowing greater exploitation of the capabilities of PCIe.

Abstract: Methods and apparatus for calibration of interface operation of a display device. In one exemplary embodiment of the invention, an embedded DisplayPort (eDP) source element (such as a graphics processing unit (GPU)) configures itself to support the minimum requirements necessary to support a sink element (such as a screen display). Unlike prior art solutions, minimum sink requirements are identified during a calibration process, and the source is configured accordingly. By tailoring the source to the specific requirements of the sink, the device can initialize faster, consume less power, etc. Moreover, in another aspect of the present invention, if a device does not initialize to an expected configuration based on prior calibration settings, the device can be flagged as having faulty or failing components.

Abstract: The present invention provides a method for generating random jitter test patterns by generating a sequence of maximum-size asynchronous packets according to the P1394b standard and transmitting the sequence to the device under test. The present invention provides a method for generating jitter test patterns by disabling the transmitter data scrambler of the second device; clearing the port_error register of the device under test; and sending a test pattern to said device under test. The present invention provides for a method for generating supply noise test patterns comprising: transmitting a test pattern to the DUT comprising a maximum length asynchronous packet containing alternate 0016 and FF16 bytes.

Abstract: A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon occurrence of a cycle synchronization event on the local portal; the peer portal sampling its local cycle timer to obtain a sample value when the peer portal receives the synchronization signal; a bridge manager at an upstream portal communicating the sample value to a bridge manager at an alpha portal; the bridge manager at the alpha portal using the sampled time value to compensate for delays through a bridge fabric, calculate the correction to be applied to a cycle timer associated with the alpha portal, and correct the cycle timer.

Abstract: Methods and apparatus for adjusting the operation of a display device so as to be at least within prescribed form factor or other constraints. In one embodiment of the invention, various operational parameters for a display element are adjusted based on considerations specific to high density form factor constraints. For example, in one such device, a Low Power DisplayPort (LPDP) device having a LPDP source and sink adjust the data rate of the visual data to minimize power consumption while still properly supporting display panel resolutions. In some embodiments, the LPDP source and sink may adjust the transceiver voltages to minimize power consumption. In an alternate embodiment, an LPDP device adjusts data rates to minimize the effects of platform noise. In another aspect of the invention, various display elements of a device coordinate quiescent (“quiet”) mode operation during periods of inactivity.

Abstract: Circuits, methods, and apparatus for registers to store information that may be used by devices in a display system. One example provides control and data registers in a display to store information pertaining to a display system that includes the display. The registers can store attributes of the display, a host device, and a branch device. The information may include an organizationally unique identifier, chip identification, major and minor chip revision information, and firmware major and minor revision information.