Patents by Inventor Colin Yates

Colin Yates has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11668062
    Abstract: A stowable flood barrier system comprising: first and second barrier modules each comprising a frame and a barrier panel pivotable with respect to the frame between a stowed position and a deployed position, in which deployed position a base of the barrier panel is sealed against the frame and a free edge of the barrier panel extends clear of the frame to present a barrier segment between lateral edges of the barrier panel, wherein the first and second barrier modules are sealable together in the deployed position along the lateral edges of their respective barrier panels to form a linked flood barrier.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: June 6, 2023
    Assignee: Flood Control International Ltd.
    Inventors: Timothy Lester Collingwood, Andrew Colin Yates, Keith Lee Stevens
  • Patent number: 11407653
    Abstract: A water quality and flow monitoring and control apparatus, method and system installed at an end user location and being capable of monitoring one or more of the following water quality parameters: microorganisms (including E. coli), mineral or other ion concentration, pH, temperature, and turbidity. The system also has a water meter that detects the flow of water and has a valve to shut the flow of water off upon detecting a fault condition such as a leak.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: August 9, 2022
    Assignee: INSTANTIA LABS, INC.
    Inventors: Colin Yates, Andre Boysen, Sam Mula
  • Publication number: 20220162821
    Abstract: A stowable flood barrier system comprising: first and second barrier modules each comprising a frame and a barrier panel pivotable with respect to the frame between a stowed position and a deployed position, in which deployed position a base of the barrier panel is sealed against the frame and a free edge of the barrier panel extends clear of the frame to present a barrier segment between lateral edges of the barrier panel, wherein the first and second barrier modules are sealable together in the deployed position along the lateral edges of their respective barrier panels to form a linked flood barrier.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 26, 2022
    Inventors: Timothy Lester Collingwood, Andrew Colin Yates, Keith Lee Stevens
  • Publication number: 20190135657
    Abstract: A water quality and flow monitoring and control apparatus, method and system installed at an end user location and being capable of monitoring one or more of the following water quality parameters: microorganisms (including E. coli), mineral or other ion concentration, pH, temperature, and turbidity. The system also has a water meter that detects the flow of water and has a valve to shut the flow of water off upon detecting a fault condition such as a leak.
    Type: Application
    Filed: May 26, 2017
    Publication date: May 9, 2019
    Applicant: INSTANTIA LABS INC.
    Inventors: Colin YATES, Andre BOYSEN, Sam MULA
  • Patent number: 7313508
    Abstract: The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: December 25, 2007
    Assignee: LSI Corporation
    Inventors: Ebo Croffie, Colin Yates, Nicholas Eib, Christopher Neville, Mario Garza, Neal Callan
  • Publication number: 20060281287
    Abstract: A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.
    Type: Application
    Filed: December 14, 2005
    Publication date: December 14, 2006
    Inventors: Colin Yates, Christopher Neville
  • Publication number: 20060264053
    Abstract: A method of forming an aligned connection between a nanotube layer and an etched feature is disclosed. An etched feature is formed having a top and a side and optionally a notched feature at the top. A patterned nanotube layer is formed such that the nanotube layer contacts portions of the side and overlaps a portion of the top of the etched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature.
    Type: Application
    Filed: December 14, 2005
    Publication date: November 23, 2006
    Inventor: Colin Yates
  • Publication number: 20040128118
    Abstract: The invention provides a method of performing process window compliant corrections of a design layout. The invention includes an operator performing the following steps: (1) simulating Develop Inspect Critical Dimension (DI CD) at best exposure conditions using the provided original layout pattern; (2) simulating DI CD at predefined boundary exposure conditions using the provided original layout pattern; (3) if the DI CD from step (1) meets the target DI CD definition, and the DI CD from step (2) meets process window specifications, convergence takes place; and (4) modifying the layout pattern and repeating steps (2) through (3) until DI CD from step (2) reaches the specification limit if any portion of step (3) is not achieved.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 1, 2004
    Inventors: Ebo Croffie, Colin Yates, Nicholas Eib, Christopher Neville, Mario Garza, Neal Callan
  • Patent number: 6458508
    Abstract: Increased resolution is available from acid-catalyzed photoresist used in fabricating integrated circuits by inhibiting chemically-basic contaminants from contacting the photoresist placed above an IC structure which emits those chemically-basic contaminants. The inhibition can result from physical barrier characteristics of a barrier layer placed between the contaminant-emitting surface and the overlying layer of photoresist, or the layer of barrier material may contain acid moieties which chemically neutralize the emitted chemically-basic contaminants before the contaminants reach the photoresist.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: October 1, 2002
    Assignee: LSI Logic Corporation
    Inventors: Nicholas F. Pasch, Shumay X. Dou, Colin Yates
  • Patent number: 5863825
    Abstract: A method of providing etched alignment marks on a semiconductor workpiece that has a substantially planar surface, such as one that has been polished, for supporting accurate alignment of the workpiece in subsequent process operations. The surface of the semiconductor workpiece includes two layers of materials that abut at the workpiece surface. For example, the workpiece may include a layer of insulative material such as silicon dioxide forming several vias and a layer of conductive material such as tungsten forming plugs in the vias. The method includes etching the substantially planar surface to reduce a height of one of the materials below the height of the other material. For example, the tungstein plugs can be etched to a height that is below the height of the surrounding silicon dioxide. The location where the silicon dioxide abuts the tungsten produces a small bump. This bump then serves as an alignment mark for subsequent operations.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: January 26, 1999
    Assignee: LSI Logic Corporation
    Inventors: Nicholas F. Pasch, Marilyn Hwan, Richard Osugi, Colin Yates, Dawn Lee, Shumay Dou