Patents by Inventor Collin Borla

Collin Borla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7122870
    Abstract: A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: October 17, 2006
    Assignee: Intel Corporation
    Inventors: John Barnak, Collin Borla, Mark Doczy, Markus Kuhn, Jacob M. Jensen
  • Publication number: 20050233530
    Abstract: A technique for producing an enhanced gate structure having a silicon-nitride buffer. Embodiments relate to the structure and development of a gate structure having a silicon-nitride buffer layer deposited upon a dielectric layer, upon which a gate material, such as polysilicon, is deposited.
    Type: Application
    Filed: June 15, 2005
    Publication date: October 20, 2005
    Inventors: John Barnak, Mark Doczy, Robert Chau, Collin Borla
  • Publication number: 20050045961
    Abstract: A technique for producing an enhanced gate structure having a silicon-nitride buffer. Embodiments relate to the structure and development of a gate structure having a silicon-nitride buffer layer deposited upon a dielectric layer, upon which a gate material, such as polysilicon, is deposited.
    Type: Application
    Filed: August 29, 2003
    Publication date: March 3, 2005
    Inventors: John Barnak, Mark Doczy, Robert Chau, Collin Borla
  • Patent number: 6849509
    Abstract: A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: February 1, 2005
    Assignee: Intel Corporation
    Inventors: John Barnak, Collin Borla, Mark Doczy, Markus Kuhn, Jacob M. Jensen
  • Publication number: 20050009311
    Abstract: A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.
    Type: Application
    Filed: August 9, 2004
    Publication date: January 13, 2005
    Inventors: John Barnak, Collin Borla, Mark Doczy, Markus Kuhn, Jacob Jensen
  • Publication number: 20040108557
    Abstract: A method of forming a gate electrode is described, comprising forming a dielectric layer on a substrate, forming a first metal layer having a first work function on the dielectric layer, forming a second metal layer having a second work function on the first metal layer, such that a gate electrode is formed on the dielectric layer which has a work function that is determined from the work function of the alloy of the two types of metal. The work function of a microelectronic transistor can be varied or “tuned” depending on the precise definition and control of the metal types, layer sequence, individual layer thickness and total number of layers.
    Type: Application
    Filed: December 9, 2002
    Publication date: June 10, 2004
    Inventors: John Barnak, Collin Borla, Mark Doczy, Markus Kuhn, Jacob M. Jensen