Abstract: Embodiments for providing an arbitrary control flow architecture for an arbitrary waveform generator (AWG) are generally described herein. In some embodiments, an arbitrary control flow instruction set defines control operations for generating an arbitrary waveform. A processor is arranged to execute the arbitrary control flow instruction set from data stored in a system memory to generate an arbitrary waveform. A system memory may include a low-latency memory and a high-latency memory, wherein a cache controller may use prediction mechanisms to reduce the latency of fetching instruction and waveform data by copying that data to the low-latency memory before it is requested.