Abstract: An output stage interface circuit for interfacing with a data bus, comprising first and second rails for receiving respectively a high voltage and a low voltage from a power supply; a data output terminal; a first main switch element coupled between said terminal and the first rail and comprising a first main MOS device having a gate and an independently configurable back gate, and responsive to a first data control signal applied to the gate pulling the voltage on the data output terminal toward the first rail voltage; and a first control circuit responsive to the voltage on said terminal being pulled from a first state across a first voltage reference to a second state for coupling said back gate to said terminal and permitting coupling of the gate of said MOS device to said terminal, the first main MOS device presenting a high impedance on the terminal when its voltage is pulled to the second state.

Abstract: A voltage level shifting circuit (5) for shifting the common mode voltage of a differential signal to be within the working range of a differential input buffer circuit (3) comprises a first resistive voltage divider circuit (18) coupled between a first input terminal (10) and a voltage reference terminal (15) for receiving a voltage reference to which the common mode voltage of the level shifted differential signal is to be referenced, and a second resistive voltage divider circuit (18) coupled between a second input terminal (11) and the voltage reference terminal (15). The differential signal is applied to the first and second terminals (10,11), and the level shifted differential signal is produced on first and second output taps (17,19) of the first and second resistive voltage divider circuits (16,18) with the common mode of the level shifted differential signal referenced to the voltage reference applied to the voltage reference terminal (15).

Abstract: A voltage level shifting circuit (5) for shifting the common mode voltage of a differential signal to be within the working range of a differential input buffer circuit (3) comprises a first resistive voltage divider circuit (18) coupled between a first input terminal (10) and a voltage reference terminal (15) for receiving a voltage reference to which the common mode voltage of the level shifted differential signal is to be referenced, and a second resistive voltage divider circuit (18) coupled between a second input terminal (11) and the voltage reference terminal (15). The differential signal is applied to the first and second terminals (10,11), and the level shifted differential signal is produced on first and second output taps (17,19) of the first and second resistive voltage divider circuits (16,18) with the common mode of the level shifted differential signal referenced to the voltage reference applied to the voltage reference terminal (15).