Abstract: A circuit system includes an analog-to-digital converter circuit, a digital-to-analog converter circuit coupled to the analog-to-digital converter circuit, and a variable latency circuit coupled to a data path that includes the digital-to-analog converter circuit. The variable latency circuit generates a deterministic latency in an output signal that is based on a measured latency of the data path.

Abstract: An oversampling channelizer for processing overlapping data that includes a data storage unit, coupled to a data line that receives data values. The data storage unit includes a plurality of lanes, wherein each of the plurality of lanes includes dedicated memory locations and wires that store and transmit data values for a data vector of a data frame, and that store and transmit additional data values for a subsequent data vector of a subsequent data frame that includes a plurality of the data values from the data vector in the data frame. The oversampling channelizer includes a coefficient storage unit that stores a plurality of coefficient vectors for a plurality of coefficient frames. The oversampling channelizer includes a computation unit that computes a dot product of the data values for the data vectors of the data frame with coefficient values for coefficient vectors of a coefficient frame selected by a coefficient storage unit.

Abstract: A circuit system includes an analog-to-digital converter circuit, a digital-to-analog converter circuit coupled to the analog-to-digital converter circuit, and a variable latency circuit coupled to a data path that includes the digital-to-analog converter circuit. The variable latency circuit generates a deterministic latency in an output signal that is based on a measured latency of the data path.

Abstract: Systems, methods, and machine-readable media are provided to perform adaptive beamforming using beamformer weights that compensate for undesirable signal path delays of a phased array. Such a system may include an array of elements that receive respective signals, analog-to-digital conversion circuitry to digitize the signals, and adaptive beamforming circuitry that performs beamforming using the digitized signals. The digitized signals used by the adaptive beamforming circuitry may not be aligned in time due to differences in analog delays between the array of elements and the analog-to-digital conversion circuitry. Even so, the adaptive beamforming circuitry may generate beamformer weights that compensate for the analog delays.

Abstract: An oversampling channelizer for processing overlapping data that includes a data storage unit, coupled to a data line that receives data values. The data storage unit includes a plurality of lanes, wherein each of the plurality of lanes includes dedicated memory locations and wires that store and transmit data values for a data vector of a data frame, and that store and transmit additional data values for a subsequent data vector of a subsequent data frame that includes a plurality of the data values from the data vector in the data frame. The oversampling channelizer includes a coefficient storage unit that stores a plurality of coefficient vectors for a plurality of coefficient frames. The oversampling channelizer includes a computation unit that computes a dot product of the data values for the data vectors of the data frame with coefficient values for coefficient vectors of a coefficient frame selected by a coefficient storage unit.

Abstract: An array of antennas includes transmitter and receiver circuits. The transmitter includes a digital-to-analog converter (DAC), splitter and filter circuits, mixer circuits, and antennas. The DAC circuit converts a digital signal into an analog signal. The splitter and filter circuits separate frequencies of the analog signal into split signals. The mixer circuits multiply frequencies from the split signals by different frequencies of carrier signals to generate modulated signals that are converted by the antennas into radio frequency (RF) signals. The receiver includes antennas, mixer circuits, a summing circuit, and an analog-to-digital converter (ADC). The antennas in the receiver receive RF signals that are converted into electrical signals. The mixer circuits multiply frequencies from the electrical signals with different frequencies of carrier signals. The outputs of the mixer circuits are summed by the summing circuit to generate a summed signal that is converted to digital by the ADC.

Abstract: One embodiment relates to an apparatus for sample rate conversion. A sample rate converter is arranged to receive an input signal at an input sampling frequency and use an interpolation interval to convert the input signal to an output signal at an output sampling frequency. A rate controller is arranged to alternate between different frequency control words for use in generating the interpolation interval signal. Another embodiment relates to a method of sample rate conversion. Another embodiment relates to a rate controller circuit. Other embodiments, aspects, and features are also disclosed.

Abstract: One embodiment relates to an apparatus for sample rate conversion. A sample rate converter is arranged to receive an input signal at an input sampling frequency and use an interpolation interval to convert the input signal to an output signal at an output sampling frequency. A rate controller is arranged to alternate between different frequency control words for use in generating the interpolation interval signal. Another embodiment relates to a method of sample rate conversion. Another embodiment relates to a rate controller circuit. Other embodiments, aspects, and features are also disclosed.

Abstract: A priority scheme is provided for ports assigned to respective channel units in a channel bank. The priority scheme is based on an amount of preallocated bandwidth unused by channel unit ports. A first water level in a first bucket is associated with an amount of allotted bandwidth unused by the channel unit and a second water level in a second bucket is associated with an amount of unused allotted bandwidth exceeding an overflow level of the first bucket. A high priority value is derived from the first water level when the first water level is above zero. A medium priority value is derived from the second water level when the first water level is equal to zero. A low priority value is derived when both water levels are zero. In another aspect of the invention, the total port bandwidth utilization history is preferably accounted for. It is differentially aged to favor recent history over older history, and optionally further compensated to favor long quiet times.

Abstract: A receiving device oversamples incoming serial data using multiple phases of its system clock. The device detects an initial edge in the set of samples and selects a sample based on the location of the initial edge. A first bit is set to the value of the selected sample. A portion of the set of samples following the initial edge. If an edge is detected, then a sample is selected based upon the location of the detected edge and the next bit is set to the value of the selected sample. If an edge is not detected within this portion, then the position of the next edge is estimated. A sample is selected based upon the location of the estimated edge and the next bit is set to the value of the selected sample. The analysis is repeated for another portion of the set of samples following the newest edge.

Abstract: A priority scheme is provided for ports assigned to respective channel units in a channel bank. The priority scheme is based on an amount of preallocated bandwidth unused by channel unit ports. A first water level in a first bucket is associated with an amount of allotted bandwidth unused by the channel unit and a second water level in a second bucket is associated with an amount of unused allotted bandwidth exceeding an overflow level of the first bucket. A high priority value is derived from the first water level when the first water level is above zero. A medium priority value is derived from the second water level when the first water level is equal to zero. A low priority value is derived when both water levels are zero. In another aspect of the invention, the total port bandwidth utilization history is preferably accounted for. It is differentially aged to favor recent history over older history, and optionally further compensated to favor long quiet times.