Abstract: A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.

Abstract: The invention provides a receiver comprising a data input and a strobe input. The strobe signal transitions whenever two consecutive bits in the data signal are the same. The receiver comprises combining means for generating a recovered clock signal from a combination of the data and strobe signals. The receiver also comprises a first sampling stage arranged to sample the data signal in dependence on the recovered clock signal, the first sampling stage comprising a plurality of sampling circuits and being arranged to obtain consecutive samples of the data signal using alternating ones of the sampling circuits. A second sampling stage is arranged to sample the data from the first sampling stage in dependence on a local system clock signal.

Abstract: A processor including: a first and at least a second data processing channel with enable logic for selectively enabling the second channel; logic for generating first and second storage addresses having a variable offset therebetween based on the same one or more address operands of the same storage access instruction; and circuitry for transferring data between the first address and a register of the first data processing channel and between the second address and a corresponding register of the second channel based on a same one or more register specifier operands of the access instruction. The first data processing channel performs an operation using one or more registers of the first data processing channel, and on condition of being enabled the second channel performs the same operation using a corresponding one or more of its own registers based on the same one or more operands of the data processing instruction.

Abstract: A method, apparatus and program. The method comprises: receiving a signal comprising a sequence of encoded symbols, each corresponding to one of a plurality of possible states; for each symbol in the sequence, determining a set of state metrics each representing a probability that the respective symbol corresponds to each of the plurality of states; and decoding the signal by processing runs of recursions, using runs of forward recursions and runs of reverse recursions. The decoding comprises performing a plurality of repeated iterations over the sequence, and for each iteration: dividing the sequence into a plurality of smaller windows, processing the windows using separate runs of recursions, and performing an associated warm-up run of recursions for each window.

Abstract: A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch while one or more others perform a transfer.

Abstract: A circuit comprising: an execution unit; a plurality of addressable devices; and a data transfer engine coupled to the execution unit and to the devices, operable to fetch a plurality of descriptors under control of the execution unit, and based on each of the fetched descriptors to perform a transfer of data from a respective first to a respective second of the devices. The DMA engine comprises delay circuitry operable to block, during a delay period running from an earlier of the transfers, any later of the transfers involving at least one of the same devices as the earlier transfer, the delay circuitry being arranged to control the blocking in dependence on an indication received in one of the descriptors.

Abstract: A circuit and corresponding method for transferring data. The circuit comprises: a CPU; a plurality of addressable devices; and a DMA engine coupled to the CPU and to those devices, the DMA engine comprising a plurality of DMA contexts each having fetch circuitry for fetching a DMA descriptor indicated by the CPU and transfer circuitry for transferring data from one to another of the devices based on a fetched descriptor. The DMA engine further comprises switching means operable to control a group of the contexts to alternate in a complementary sequence between fetching and performing a transfer, such that alternately one or more contexts in the group fetch whilst one or more others perform a transfer.

Abstract: The invention provides a receiver comprising a data input and a strobe input. The strobe signal transitions whenever two consecutive bits in the data signal are the same. The receiver comprises combining means for generating a recovered clock signal from a combination of the data and strobe signals. The receiver also comprises a first sampling stage arranged to sample the data signal in dependence on the recovered clock signal, the first sampling stage comprising a plurality of sampling circuits and being arranged to obtain consecutive samples of the data signal using alternating ones of the sampling circuits. A second sampling stage is arranged to sample the data from the first sampling stage in dependence on a local system clock signal.