Abstract: Buffer lines and corresponding buffer tags and buffer valid/dirty registers in conjunction with buffer control circuit are provided to a DMA controller enabling the DMA controller to conditionally pre-fetch data from memory while data being read are transferred from the DMA controller to the I/O device during read operations and to conditionally write data back to memory while data being written are transferred from the I/O device to the DMA controller during write operations, thereby improving asynchronous read/write throughputs. Read requests, random as well as sequential, are satisfied with pre-fetched data if they are validly stored. Write requests, random as well as sequential, are deferred, batched and optimized. The improved throughput is achieved in a manner completely transparent to system software.