Patents by Inventor Concetta E. Riccobene

Concetta E. Riccobene has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6765227
    Abstract: A semiconductor-on-insulator (SOI) wafer. The wafer includes a silicon substrate, a buried oxide (BOX) layer disposed on the substrate, and an active layer disposed on the box layer. The active layer has an upper silicon layer disposed on a silicon-germanium layer. The silicon-germanium layer is disposed on a lower silicon layer. The silicon-germanium of the silicon-germanium layer is strained silicon-germanium and is about 200 Å to about 400 Å thick.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: July 20, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bin Yu, William G. En, Judy Xilin An, Concetta E. Riccobene
  • Patent number: 6717212
    Abstract: A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: April 6, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Dong-Hyuk Ju, William George En, Srinath Krishnan, Concetta E. Riccobene, Zoran Krivokapic, Judy Xilin An, Bin Yu
  • Patent number: 6538284
    Abstract: A transistor on an SOI wafer has a subsurface recombination area within its body. The recombination area includes one or more doped subsurface islands, the doped islands having the same conductivity type as that of a source and a drain on opposite sides of the body, and having an opposite conductivity type from the remainder of the body. The doped subsurface island(s) may be formed by a doping implant into a surface semiconductor layer, for example through an open portion of a doping mask, the opening portion created for example by removal of a dummy gate. The doping of the islands may be performed so that the doping level of the island(s) is approximately the same as that of the body, thus enabling both Shockley-Read-Hall (SRH) and Auger recombination to take place.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: March 25, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Concetta E. Riccobene, Dong-Hyuk Ju
  • Patent number: 6525378
    Abstract: A semiconductor device and a method of forming same are disclosed. The device includes an SOI wafer including a semiconductor layer, a substrate and a buried insulator layer therebetween. The semiconductor layer includes a source region, a drain region, and a body region disposed between the source and drain regions. At least one of the source and drain regions includes an epitaxially raised region. A gate is on the semiconductor layer, the gate being operatively arranged with the source, drain, and body regions to form a transistor. The at least one of the source and drain regions including the epitaxially raised region includes a silicide region spaced apart from the body region by about 200 to about 1000 Angstroms.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: February 25, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Concetta E. Riccobene
  • Patent number: 6515333
    Abstract: According to the invention, a silicon-on-insulator (SOI) device and a method of constructing the device is disclosed. The SOI device has a substrate with a BOX layer disposed on the upper surface of the substrate. The BOX has an upper surface and a cavity extending from the upper surface partially therein. An active layer is disposed on the upper surface of BOX layer and extends into the cavity.
    Type: Grant
    Filed: April 27, 2001
    Date of Patent: February 4, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Concetta E. Riccobene
  • Patent number: 6479868
    Abstract: A silicon-on-insulator (SOI) transistor. The SOI transistor includes a germanium implanted source and drain having a body disposed therebetween, and a gate disposed on the body, the germanium being implanted at an angle such that the source has a concentration of germanium at a source/body junction and the gate shields germanium implantation in the drain adjacent a drain/body junction resulting in a graduated drain/body junction. Also disclosed is a method of fabricating the SOI transistor.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: November 12, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Xilin Judy An, Bin Yu, Concetta E. Riccobene
  • Patent number: 6410371
    Abstract: A method of forming a semiconductor-on-insulator (SOI) wafer. The method includes the steps of providing a first wafer, the first wafer having a silicon substrate and an oxide layer disposed thereon; providing a second wafer, the second wafer having a silicon substrate, the substrate of the second wafer having a silicon-germanium layer disposed thereon, a silicon layer disposed on the silicon-germanium layer and an oxide layer disposed on the silicon layer; wafer bonding the first and second wafers; and removing an undesired portion of the substrate from the second wafer to form an upper silicon layer. The resulting SOI wafer structure is also disclosed.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: June 25, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bin Yu, William G. En, Judy Xilin An, Concetta E. Riccobene