Abstract: A gating-based receiver circuit is provided. The receiver circuit includes a gating signal generator, receiving a first and second input signals and reference voltage to output a gating signal, wherein an adaptive reference voltage is generated by the first and second input signals and the reference voltage; and a receiver, receiving the first and second input signals and the gating signal to provide a receiver output signal. In response to both the first input signal and the second input signal being higher than the adaptive reference voltage, the gating signal disables the receiver, and in response to one of the first input signal and the second input signal being lower than the adaptive reference voltage, the gating signal enables the receiver.

Abstract: A gating-based receiver circuit is provided. The receiver circuit includes a gating signal generator, receiving a first and second input signals and reference voltage to output a gating signal, wherein an adaptive reference voltage is generated by the first and second input signals and the reference voltage; and a receiver, receiving the first and second input signals and the gating signal to provide a receiver output signal. In response to both the first input signal and the second input signal being higher than the adaptive reference voltage, the gating signal disables the receiver, and in response to one of the first input signal and the second input signal being lower than the adaptive reference voltage, the gating signal enables the receiver.

Abstract: A signal equalization method includes: receiving a clock signal and a first reference signal; detecting a phase and a frequency of the clock signal based on the first reference signal to generate a detection result; generating a speed judgement signal according to the detection result; and, receiving the speed judgement signal and deciding an equalizer operation parameter according to the speed judgement signal.

Abstract: A single ended receiver includes a current mode logic circuit, a differential to single amplifier, and a voltage detector. The current mode logic circuit is configured to receive an input signal and a reference voltage value and is configured to output a first output signal. The differential to single amplifier is coupled to the current mode logic circuit and is configured to receive the first output signal and to output a second output signal. The voltage detector is coupled to the differential to single amplifier and is configured to output a control signal to the differential to single amplifier according to the reference voltage value. The differential to single amplifier is further configured to adjust a voltage value of the differential to single amplifier internal signal according to the control signal, so that a duty cycle of the second output signal is adjusted.