Abstract: Disclosed is a method and circuit for generating an average binary code from at least two input binary codes. The circuit may be employed in an integrated circuit having first and second circuits for generating binary codes am-1:0 and bm-1:0, respectively. In one embodiment, the circuit asynchronously generates a binary code cm-1:0 representing an average of the binary codes am-1:0 and bm-1:0 generated by the first and second circuits, respectively.

Abstract: Disclosed is a method and circuit for variably controlling a delay line for a read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input strobe signal. The variably controlled delay circuit also receives a multibit control code. The variably controlled delay circuit transmits the input strobe signal after a time delay, wherein the time delay varies according to the multibit control code. The FIFO is coupled to the variably controlled delay circuit and receives the time delayed strobe signal therefrom. The FIFO receives an input data bit signal. The FIFO stores the input data bit signal in response to receiving the time delayed strobe signal.

Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: Disclosed is a high voltage decoupling capacitor-biasing circuit with no dc current. In one embodiment, the circuit includes a power supply node, a ground node, a common node, a first p-channel FET, a first n-channel FET, and a common node biasing circuit. The first p-channel FET includes a source, gate, and drain, wherein the source and drain of the first p-channel FET are coupled to the power supply node, and wherein the gate of the first p-channel FET is coupled to the common node. The first n-channel FET includes a source, gate, and drain, wherein the source and drain of the first n-channel FET are coupled to the ground node, and wherein the gate of the first n-channel FET is coupled to the common node. The common node biasing circuit is coupled between the power supply and ground nodes. The common node biasing circuit is configured to maintain the common node at a predetermined voltage above ground by charging up or charging down the common node.

Abstract: Disclosed is an input/output (IO) device having a power supply node, an input node for receiving an input data signal, and an output node for outputting an output data signal generated in response to the input node receiving the input data bit signal. The IO device also includes a pull-up driver coupled to the power supply node and the output node, wherein the pull-up driver comprises an impedance at the output node which is constant for all voltages at the output node. Additionally, the IO device may have a circuit coupled to the input node, the pull-up driver, and the output node. This circuit is configured to generate a signal that is provided to the pull-up driver. The signal generated by the circuit varies as a function of the voltage at the output node.

Abstract: Disclosed is an input/output (IO) device for transmitting a data bit signal. In one embodiment, the IO device includes an IO device input node for receiving an input data bit signal and an IO device output node. Additionally, the IO device includes a plurality of drivers coupled between the IO device input and output nodes, each having first and second n-channel FETs coupled together, first and second p-channel FETs coupled together. A drain of each driver's second n-channel FET and each driver's first p-channel FET is coupled to the IO device output node, while a gate of each driver's first n-channel FET is coupled to the IO device input node.

Abstract: Disclosed is a method and circuit for generating an average binary code from at least two input binary codes. The circuit may be employed in an integrated circuit having first and second circuits for generating binary codes am−1:0 and bm−1:0, respectively. In one embodiment, the circuit asynchronously generates a binary code cm−1:0 representing an average of the binary codes am−1:0 and bm−1:0 generated by the first and second circuits, respectively.

Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: Disclosed is a method and circuit for variably controlling a delay line for read data capture timing window. In one embodiment, the circuit includes a variably controlled delay circuit coupled to a FIFO. The variably controlled delay circuit receives an input strobe signal. The variably controlled delay circuit also receives a multibit control code. The variably controlled delay circuit transmits the input strobe signal after a time delay, wherein the time delay varies according to the multibit control code. The FIFO is coupled to the variably controlled delay circuit and receives the time delayed strobe signal therefrom. The FIFO is receives an input data bit signal. The FIFO stores the input data bit signal in response to receiving the time delayed strobe signal.

Abstract: Disclosed is a high voltage decoupling capacitor-biasing circuit with no dc current. In one embodiment, the circuit includes a power supply node, a ground node, a common node, a first p-channel FET, a first n-channel FET, and a common node biasing circuit. The first p-channel FET includes a source, gate, and drain, wherein the source and drain of the first p-channel FET are coupled to the power supply node, and wherein the gate of the first p-channel FET is coupled to the common node The first n-channel FET includes a source, gate, and drain, wherein the source and drain of the first n-channel FET are coupled to the ground node, and wherein the gate of the first n-channel FET is coupled to the common node. The common node biasing circuit is coupled between the power supply and ground nodes. The common node biasing circuit is configured to maintain the common node at a predetermined voltage above ground by charging up or charging down the common node.

Abstract: Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit.

Abstract: Disclosed is an input/output (IO) device for transmitting a data bit signal. In one embodiment, the IO device includes an IO device input node for receiving an input data bit signal and an IO device output node. Additionally, the IO device includes a plurality of drivers coupled between the IO device input and output nodes, each having first and second n-channel FETs coupled together, first and second p-channel FETs coupled together. A drain of each driver's second n-channel FET and each driver's first p-channel FET is coupled to the IO device output node, while a gate of each driver's first n-channel FET is coupled to the IO device input node.

Abstract: The present invention describes a method and apparatus to reduce the delay variations caused by the process variations in DDR input buffers. The changes in the impedance due to the process variations are used to determine the bias current for the DDR buffers. The bias current is proportional to the changes in the impedance. The bias current is adjusted to maintain small delay variations in the DDR buffers. The delays in the DDR buffers can be adjusted by adjusting the bias current in response to the corresponding impedance changes due to the process variations in the semiconductor devices.

Abstract: Disclosed is an input/output (IO) device for transmitting a data bit signal. In one embodiment, the IO device includes an IO device input node for receiving an input data bit signal, an IO device output node, and a common ground node. The IO device also includes a first driver having first and second n-channel FETs coupled together, first and second p-channel FETs coupled together, a plurality of third n-channel or p-channel FETs each having a drain coupled to the IO device input node, and a plurality of first capacitors coupled between the common ground node and respective sources of the plurality of third n-channel or p-channel FETs. The drains of the first p-channel FET and the second n-channel FET are coupled to the IO device output node, while the gate of the first n-channel FET is coupled to the IO device input node.

Abstract: A method and system for reducing coupling capacitance interference between adjacent transmission lines in an electrical circuit. The method and system includes the use of inverter and buffer devices that are laid out along signal paths carrying signal transmissions to assure that a portion of signal transmission between devices has zero coupling capacitance, yet provides for a net coupling capacitance of one.

Abstract: A self-tracking sense amplifier strobing circuit and process to provide a sense amplifier enable signal in order to reliably control memory read operations over a wide variety of processing conditions. An array of self-tracking memory cells is configured to store a fixed value and includes at least a first tracking cell coupled to receive a wordline enable signal. First and second bitlines are coupled to the first array with the first bitline to be coupled to a power source. An output coupled to the second bitline is asserted to provide a sense amplifier enable signal when the second bitline reaches a predetermined voltage in response to the wordline enable signal being received by the tracking cell.

Abstract: A self-tracking write pulse control circuit to determine the time provided to complete a write operation to a memory. A tracking array including at least a first tracking memory cell configured on the memory includes an output and stores a default value. First and second bitlines are coupled to the tracking memory cell. A write multiplexor circuit is coupled to the first and second bitlines and coupled to receive an enable signal which concurrently initiates a write pulse. A write multiplexor circuit writes a different value to the tracking memory cell in response to receiving the enable signal. The output of the tracking memory cell transitions to end the write pulse when the different value has been successfully written to the tracking memory cell.

Abstract: A sense amplifier for detecting the difference in voltage between two bitlines of a memory circuit. The sense amplifier is comprised of a differential amplifier which is coupled to the two bitlines and generates an output signal based on voltage levels sensed in the bitlines. The differential amplifier is coupled to V.sub.CC and ground through an active load and a current source respectively. To address the problem of increased common mode voltage levels found in the bitlines, a pair of transistors are connected in parallel across the active load to V.sub.CC and the differential amplifier. The gate of one of the transistors is coupled to one of the bitlines and the gate of the other one of the transistors is coupled to the other one of the bitlines. With these two transistors coupled in parallel across the load as described, the differential amplifier has increased immunity to elevated common mode levels found in the bitlines.

Abstract: A high speed, static, BiCMOS comparator circuit. Though static, the circuit operates at nearly dynamic speeds. The circuit consists of two stages. The first stage generates XOR and XNOR outputs given two bit strings. The second stage detects hit and miss separately using the XOR and XNOR inputs. The second stage generates signals for both hit lines and miss lines.