Patents by Inventor Cong-Son Trinh

Cong-Son Trinh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7763940
    Abstract: An electronic device having an LV-well element trigger structure that reduces the effective snapback trigger voltage in MOS drivers or ESD protection devices. A reduced triggering voltage facilitates multi-finger turn-on and thus uniform current flow and/or helps to avoid competitive triggering issues.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: July 27, 2010
    Assignee: Sofics BVBA
    Inventors: Markus Paul Josef Mergens, Bart Keppens, Koen Verhaege, John Armer, Cong Son Trinh
  • Patent number: 7414273
    Abstract: A two-dimensional silicon controlled rectifier (2DSCR) having the anode and cathode forming a checkerboard pattern. Such a pattern maximizes the anode to cathode contact length (the active area) within a given SCR area, i.e., effectively increasing the SCR width. Increasing the physical SCR area, increases the current handling capabilities of the SCR.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: August 19, 2008
    Assignees: Sarnoff Corporation, Sarnoff Europe
    Inventors: Russell Mohn, Cong-Son Trinh, Phillip Czeslaw Jozwiak, John Armer, Markus Paul Josef Mergens
  • Publication number: 20060011939
    Abstract: A two-dimensional silicon controlled rectifier (2DSCR) having the anode and cathode forming a checkerboard pattern. Such a pattern maximizes the anode to cathode contact length (the active area) within a given SCR area, i.e., effectively increasing the SCR width. Increasing the physical SCR area, increases the current handling capabilities of the SCR.
    Type: Application
    Filed: July 7, 2005
    Publication date: January 19, 2006
    Inventors: Russell Mohn, Cong-Son Trinh, Phillip Jozwiak, John Armer, Markus Mergens
  • Patent number: 6909149
    Abstract: A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: June 21, 2005
    Assignees: Sarnoff Corporation, Sarnoff Europe BVBA
    Inventors: Cornelius Christian Russ, Phillip Czeslaw Jozwiak, Markus Paul Josef Mergens, John Armer, Cong-Son Trinh, Russell Mohn, Koen Gerard Maria Verhaege
  • Publication number: 20040207021
    Abstract: A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages.
    Type: Application
    Filed: April 15, 2004
    Publication date: October 21, 2004
    Inventors: Cornelius Christian Russ, Phillip Czeslaw Jozwiak, Markus Paul Josef Mergens, John Armer, Cong-Son Trinh, Russell Mohn, Koen Gerard Maria Verhaege