Patents by Inventor Cong-Wei CHEN

Cong-Wei CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND APPARATUS FOR FLATTENING WORKPIECE
    Publication number: 20260130159
    Abstract: A method for manufacturing a semiconductor package and an apparatus for flattening a workpiece are provided. The method includes providing a panel over a stage, wherein the panel includes a lower surface facing the stage and an upper surface opposite to the lower surface; applying a first force to a first region of the upper surface of the panel along at least one direction from the panel toward the stage; and transferring the first force from the first region to a second region of the upper surface of the panel different from the first region.
    Type: Application
    Filed: December 30, 2025
    Publication date: May 7, 2026
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ya Fang CHAN, Cong-Wei CHEN, Kuoching CHENG, Shih-Yu WANG
  • Method for manufacturing semiconductor package and apparatus for flattening workpiece
    Patent number: 12512337
    Abstract: A method for manufacturing a semiconductor package and an apparatus for flattening a workpiece are provided. The method includes providing a panel over a stage, wherein the panel includes a lower surface facing the stage and an upper surface opposite to the lower surface; applying a first force to a first region of the upper surface of the panel along at least one direction from the panel toward the stage; and transferring the first force from the first region to a second region of the upper surface of the panel different from the first region.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: December 30, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ya Fang Chan, Cong-Wei Chen, Kuoching Cheng, Shih-Yu Wang
  • METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND APPARATUS FOR FLATTENING WORKPIECE
    Publication number: 20240249958
    Abstract: A method for manufacturing a semiconductor package and an apparatus for flattening a workpiece are provided. The method includes providing a panel over a stage, wherein the panel includes a lower surface facing the stage and an upper surface opposite to the lower surface; applying a first force to a first region of the upper surface of the panel along at least one direction from the panel toward the stage; and transferring the first force from the first region to a second region of the upper surface of the panel different from the first region.
    Type: Application
    Filed: January 20, 2023
    Publication date: July 25, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ya Fang CHAN, Cong-Wei CHEN, Kuoching CHENG, Shih-Yu WANG
  • Semiconductor package structure having a protection layer
    Patent number: 10211161
    Abstract: A semiconductor package structure includes a semiconductor substrate, at least one semiconductor die, an encapsulant, a protection layer, a plurality of conductive elements and a redistribution layer. The semiconductor die is disposed on the semiconductor substrate. The encapsulant covers at least a portion of the semiconductor die, and has a first surface and a lateral surface. The protection layer covers the first surface and the lateral surface of the encapsulant. The conductive elements surround the lateral surface of the encapsulant. The redistribution layer electrically connects the semiconductor die and the conductive elements.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: February 19, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuan-Feng Chiang, Cong-Wei Chen, I-Ting Chi, Shao-An Chen
  • SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20180061767
    Abstract: A semiconductor package structure includes a semiconductor substrate, at least one semiconductor die, an encapsulant, a protection layer, a plurality of conductive elements and a redistribution layer. The semiconductor die is disposed on the semiconductor substrate. The encapsulant covers at least a portion of the semiconductor die, and has a first surface and a lateral surface. The protection layer covers the first surface and the lateral surface of the encapsulant. The conductive elements surround the lateral surface of the encapsulant. The redistribution layer electrically connects the semiconductor die and the conductive elements.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 1, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuan-Feng CHIANG, Cong-Wei CHEN, I-Ting CHI, Shao-An CHEN