Abstract: An embodiment of the present application discloses an array substrate and a liquid crystal display panel. The array substrate uses a first barrier layer including a first aperture in an aperture region. The first barrier layer is at least correspondingly disposed in a thin film transistor disposing region and a gate driver on array circuit region. The first barrier layer is configured to block the alkaline cation from spreading along a direction to the active layer. Along a direction at a right angle from the substrate to the active layer, a depth by which the alkaline cation enters the first barrier layer is less than or equal to 20 ?.

Abstract: An embodiment of the present application discloses an array substrate and a liquid crystal display panel. The array substrate uses a first barrier layer including a first aperture in an aperture region. The first barrier layer is at least correspondingly disposed in a thin film transistor disposing region and a gate driver on array circuit region. The first barrier layer is configured to block the alkaline cation from spreading along a direction to the active layer. Along a direction at a right angle from the substrate to the active layer, a depth by which the alkaline cation enters the first barrier layer is less than or equal to 20 ?.

Abstract: The present application provides an array substrate, a display panel, and a display device. In the present application, a plurality of first-type data lines and a plurality of second-type data lines with data voltages of opposite polarities are provided, and a light-shielding layer of each of first sub-pixels is at least electrically connected to a light-shielding layer of one of second sub-pixels through a connecting line, which can effectively reduce a change in pixel brightness caused by capacitive coupling, and relieve a problem of image flicker.

Abstract: An array substrate is provided. The array substrate includes a substrate, a light-shielding layer, and an active layer. The light-shielding layer is disposed on the substrate, and the active layer is disposed on the light-shielding layer. Wherein, an orthographic projection of the active layer on the substrate is positioned within an orthographic projection of the light-shielding layer on the substrate. The present disclosure prevents the active layer from forming ramps and then breaking by allowing the orthographic projection of the active layer on the substrate to be positioned within the orthographic projection of the light-shielding layer on the substrate, thereby ensuring performances of the array substrate.

Abstract: A display panel and a display device are disclosed. The display panel includes a transistor disposed in the non-display area. The transistor includes a charge inducing layer, and a first insulating layer, an active layer, a second insulating layer, and a gate electrode all disposed on the charge inducing layer, so that the actively layer, the gate electrode, and the charge inducing layer collectively form a capacitance system, which benefits extending of the conduction time of the transistor, thereby giving a boost to an increase in a charging rate of the data line, and ensuring a smooth display of the display panel.

Abstract: A display panel and a display device are disclosed. The display panel includes a transistor disposed in the non-display area. The transistor includes a charge inducing layer, and a first insulating layer, an active layer, a second insulating layer, and a gate electrode all disposed on the charge inducing layer, so that the actively layer, the gate electrode, and the charge inducing layer collectively form a capacitance system, which benefits extending of the conduction time of the transistor, thereby giving a boost to an increase in a charging rate of the data line, and ensuring a smooth display of the display panel.