Abstract: An array substrate is provided. The array substrate includes a substrate, a light-shielding layer, and an active layer. The light-shielding layer is disposed on the substrate, and the active layer is disposed on the light-shielding layer. Wherein, an orthographic projection of the active layer on the substrate is positioned within an orthographic projection of the light-shielding layer on the substrate. The present disclosure prevents the active layer from forming ramps and then breaking by allowing the orthographic projection of the active layer on the substrate to be positioned within the orthographic projection of the light-shielding layer on the substrate, thereby ensuring performances of the array substrate.

Abstract: A display panel and a display device are disclosed. The display panel includes a transistor disposed in the non-display area. The transistor includes a charge inducing layer, and a first insulating layer, an active layer, a second insulating layer, and a gate electrode all disposed on the charge inducing layer, so that the actively layer, the gate electrode, and the charge inducing layer collectively form a capacitance system, which benefits extending of the conduction time of the transistor, thereby giving a boost to an increase in a charging rate of the data line, and ensuring a smooth display of the display panel.

Abstract: A display panel and a display device are disclosed. The display panel includes a transistor disposed in the non-display area. The transistor includes a charge inducing layer, and a first insulating layer, an active layer, a second insulating layer, and a gate electrode all disposed on the charge inducing layer, so that the actively layer, the gate electrode, and the charge inducing layer collectively form a capacitance system, which benefits extending of the conduction time of the transistor, thereby giving a boost to an increase in a charging rate of the data line, and ensuring a smooth display of the display panel.