Abstract: Disclosed in the present disclosure are a transistor device and a memory. The transistor device comprises: a gate; a semiconductor channel, which surrounds a surface of the gate, wherein the semiconductor channel comprises a multi-layer thin film structure, and the multi-layer thin film structure comprises an indium oxide thin film layer, a gallium oxide thin film layer and a zinc oxide thin film layer; a first source drain, which is disposed at a first end of the semiconductor channel; and a second source drain, which is disposed at a second end of the semiconductor channel. By means of the present disclosure, the control ability of the turn-off of the semiconductor channel and the mobility of the semiconductor channel can be adjusted and balanced.

Abstract: Disclosed herein are a field effect transistor and a preparation method therefor, and a memory and a display. The field effect transistor comprises: a first source/drain layer (1), an insulating layer (2) and a second source/drain layer (3), which are sequentially stacked; and a gate electrode (5) and a channel layer (4), which surrounds the gate electrode (5), wherein the gate electrode (5) and the channel layer (4) are located in the second source/drain layer (3) and the insulating layer (2), and the channel layer (4) is in contact with the first source/drain layer (1) and the second source/drain layer (3). The channel layer (4) comprises an outer layer and an inner layer (42), wherein the inner layer (42) is close to the gate electrode (5); the outer layer is in contact with the insulating layer (2), the first source/drain layer (1) and the second source/drain layer (3); and both the outer layer and the inner layer (42) are made of indium oxide.

Abstract: Disclosed herein are a thin-film transistor and a preparation method therefor, and a memory and a display. The thin-film transistor comprises a first source/drain layer (1); a second source/drain layer (3); an insulating layer (2), which is located between the first source/drain layer (1) and the second source/drain layer (3); a channel layer (4), which is embedded in the first source/drain layer (1) and the insulating layer (2); and a gate electrode (5), which is embedded in the channel layer (4), wherein an embedded end of the channel layer (4) is in contact with the second source/drain layer (3), and a top end of the channel layer (4) and a top end of the gate electrode (5) are both flush with the first source/drain layer (1).

Abstract: Disclosed are a thin-film transistor and a preparation method therefor, and a memory and a display.

Abstract: A thin film transistor and a preparation method therefor, a memory, and a display. The thin film transistor comprises: a first source/drain layer (1), a first insulating layer (2), a second source/drain layer (3) and a second insulating layer (4) which are sequentially stacked; and a gate (6) and a channel layer (5) surrounding the gate (6), which are located in the second insulating layer (4), the second source/drain layer (3) and the first insulating layer (2). The channel layer (5) is in contact with the first source/drain layer (1), the first insulating layer (2), the second source/drain layer (3) and the second insulating layer (4). The thin film transistor is a CAA architecture of an annular channel surrounding the gate (6). Moreover, the leakage current of the gate (6) and the parasitic capacitance of the thin film transistor can be reduced by adding the second insulating layer (4) above the second source/drain layer (3).

Abstract: A pressure sensor based on zinc oxide nanowires and a method of manufacturing a pressure sensor based on zinc oxide nanowires are provided. The manufacturing method includes: manufacturing a bottom electrode on a substrate; manufacturing a seed layer on the bottom electrode; manufacturing a zinc oxide nanowire layer on the seed layer; manufacturing a support layer on the zinc oxide nanowire layer; and manufacturing a top electrode on the support layer.

Abstract: Disclosed are a transistor device and a memory. The transistor device comprises: a gate; a gate insulating layer, covering the surface of the gate; a semiconductor channel, covering the surface of the gate insulating layer away from the gate; a first source drain, surrounding the side of the gate insulating layer away from the gate and located at a first end of the gate; and a second source drain, arranged on the side of the gate insulating layer away from the gate and located at a second end of the gate. According to the transistor device structure formed in the present disclosure, a semiconductor channel-all-around gate is formed, the area corresponding to the semiconductor channel and the gate is increased, the control capability of the gate with respect to the semiconductor channel is effectively enhanced, and the size of the device can be further reduced.

Abstract: A pressure sensor based on zinc oxide nanowires and a method of manufacturing a pressure sensor based on zinc oxide nanowires are provided. The manufacturing method includes: manufacturing a bottom electrode on a substrate; manufacturing a seed layer on the bottom electrode; manufacturing a zinc oxide nanowire layer on the seed layer; manufacturing a support layer on the zinc oxide nanowire layer; and manufacturing a top electrode on the support layer.

Abstract: A method for obtaining a contact resistance of a planar device includes: obtaining a contact resistance of a planar device by using a potential measurement method, in the measurement of the surface potential distribution, the planar device is in a state of current flowing, a certain voltage drop is formed at a junction area of the device; extracting the voltage drop measured through the Kelvin microscope by using a linear fitting method; and dividing the measured voltage drop by the current flowing through the device, thereby accurately calculating the magnitude of the contact resistance at the junction area of the planar device. With the present invention, the contact resistance of the planar device can be precisely measured, which is suitable for the contact resistance measurement experiments of devices such as thin film transistors and diodes.

Abstract: A method for obtaining a contact resistance of a planar device includes: obtaining a contact resistance of a planar device by using a potential measurement method, in the measurement of the surface potential distribution, the planar device is in a state of current flowing, a certain voltage drop is formed at a junction area of the device; extracting the voltage drop measured through the Kelvin microscope by using a linear fitting method; and dividing the measured voltage drop by the current flowing through the device, thereby accurately calculating the magnitude of the contact resistance at the junction area of the planar device. With the present invention, the contact resistance of the planar device can be precisely measured, which is suitable for the contact resistance measurement experiments of devices such as thin film transistors and diodes.