Patents by Inventor Connie Cheung

Connie Cheung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10492702
    Abstract: Methods of cortical mapping in real-time are provided. Aspects of the methods include performing real-time processing of signals indicative of a subject's brain activity by applying one filter or more to the signals, wherein the processing is in the absence of averaging based on time. Systems for cortical mapping in real-time are also provided. The methods and systems are useful in research, diagnostic, and therapeutic applications.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 3, 2019
    Assignee: The Regents of the University of California
    Inventors: Edward Chang, Connie Cheung
  • Publication number: 20150313497
    Abstract: Methods of cortical mapping in real-time are provided. Aspects of the methods include performing real-time processing of signals indicative of a subject's brain activity by applying one filter or more to the signals, wherein the processing is in the absence of averaging based on time. Systems for cortical mapping in real-time are also provided. The methods and systems are useful in research, diagnostic, and therapeutic applications.
    Type: Application
    Filed: January 30, 2013
    Publication date: November 5, 2015
    Applicant: The Regents of the University of California
    Inventors: Edward Chang, Connie Cheung
  • Patent number: 8464009
    Abstract: A distributed shared memory multiprocessor system that supports both fine- and coarse- grained interleaving of the shared memory address space. A ceiling mask sets a boundary between the fine-grain interleaved and coarse-grain interleaved memory regions of the distributed shared memory. A method for satisfying a memory access request in a distributed shared memory subsystem of a multiprocessor system having both fine- and coarse-grain interleaved memory segments. Certain low or high order address bits, depending on whether the memory segment is fine- or coarse-grain interleaved, respectively, are used to determine if the memory address is local to a processor node. A method for setting the ceiling mask of a distributed shared memory multiprocessor system to optimize performance of a first application run on a single node and performance of a second application run on a plurality of nodes.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: June 11, 2013
    Assignee: Oracle America, Inc.
    Inventors: Ramaswamy Sivaramakrishnan, Connie Cheung, William Bryg
  • Publication number: 20090307434
    Abstract: A distributed shared memory multiprocessor system that supports both fine- and coarse-grained interleaving of the shared memory address space. A ceiling mask sets a boundary between the fine-grain interleaved and coarse-grain interleaved memory regions of the distributed shared memory. A method for satisfying a memory access request in a distributed shared memory subsystem of a multiprocessor system having both fine- and coarse-grain interleaved memory segments. Certain low or high order address bits, depending on whether the memory segment is fine- or coarse-grain interleaved, respectively, are used to determine if the memory address is local to a processor node. A method for setting the ceiling mask of a distributed shared memory multiprocessor system to optimize performance of a first application run on a single node and performance of a second application run on a plurality of nodes.
    Type: Application
    Filed: June 4, 2008
    Publication date: December 10, 2009
    Applicant: Sun Microsystems, Inc.
    Inventors: Ramaswamy Sivaramakrishnan, Connie Cheung, William Bryg