Patents by Inventor Connie W. Cheung
Connie W. Cheung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11914521Abstract: A mechanism for cache quota control is disclosed. A cache memory is configured to receive access requests from a plurality of agents, wherein a given request from a given agent of the plurality of agents specifies an identification value associated with the given agent of the plurality of agents. A cache controller is coupled to the cache memory, and is configured to store indications of current allocations of the cache memory to individual ones of the plurality of agents. The cache controller is further configured to track requests to the cache memory based on identification values specified in the requests and determine whether to update allocations of the cache memory to the individual ones of the plurality of agents based on the tracked requests.Type: GrantFiled: June 29, 2022Date of Patent: February 27, 2024Assignee: Apple Inc.Inventors: Wolfgang H. Klingauf, Muhammad Umer Amjad, Connie W. Cheung, Yueh-Ta Wu, Muditha Kanchana, John H. Kelm
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Patent number: 11755489Abstract: A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.Type: GrantFiled: August 31, 2021Date of Patent: September 12, 2023Assignee: Apple Inc.Inventors: Rohit K. Gupta, Rohit Natarajan, Jurgen M. Schulz, Harshavardhan Kaushikkar, Connie W. Cheung
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Publication number: 20230064369Abstract: A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Rohit K. Gupta, Rohit Natarajan, Jurgen M. Schulz, Harshavardhan Kaushikkar, Connie W. Cheung
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Patent number: 11232033Abstract: Systems, apparatuses, and methods for dynamically partitioning a memory cache among a plurality of agents are described. A system includes a plurality of agents, a communication fabric, a memory cache, and a lower-level memory. The partitioning of the memory cache for the active data streams of the agents is dynamically adjusted to reduce memory bandwidth and increase power savings across a wide range of applications. A memory cache driver monitors activations and characteristics of the data streams of the system. When a change is detected, the memory cache driver dynamically updates the memory cache allocation policy and quotas for the agents. The quotas specify how much of the memory cache each agent is allowed to use. The updates are communicated to the memory cache controller to enforce the new policy and enforce the new quotas for the various agents accessing the memory.Type: GrantFiled: August 2, 2019Date of Patent: January 25, 2022Assignee: Apple Inc.Inventors: Wolfgang H. Klingauf, Connie W. Cheung, Rohit K. Gupta, Rohit Natarajan, Vanessa Cristina Heppolette, Varaprasad V. Lingutla, Muditha Kanchana
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Publication number: 20210034527Abstract: Systems, apparatuses, and methods for dynamically partitioning a memory cache among a plurality of agents are described. A system includes a plurality of agents, a communication fabric, a memory cache, and a lower-level memory. The partitioning of the memory cache for the active data streams of the agents is dynamically adjusted to reduce memory bandwidth and increase power savings across a wide range of applications. A memory cache driver monitors activations and characteristics of the data streams of the system. When a change is detected, the memory cache driver dynamically updates the memory cache allocation policy and quotas for the agents. The quotas specify how much of the memory cache each agent is allowed to use. The updates are communicated to the memory cache controller to enforce the new policy and enforce the new quotas for the various agents accessing the memory.Type: ApplicationFiled: August 2, 2019Publication date: February 4, 2021Inventors: Wolfgang H. Klingauf, Connie W. Cheung, Rohit K. Gupta, Rohit Natarajan, Vanessa Cristina Heppolette, Varaprasad V. Lingutla, Muditha Kanchana
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Patent number: 9323600Abstract: The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.Type: GrantFiled: September 15, 2014Date of Patent: April 26, 2016Assignee: Oracle International CorporationInventors: Ramaswamy Sivaramakrishnan, Ali Vahidsafa, Aaron S. Wynn, Connie W. Cheung
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Publication number: 20150039938Abstract: The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.Type: ApplicationFiled: September 15, 2014Publication date: February 5, 2015Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Ramaswamy Sivaramakrishnan, Ali Vahidsafa, Aaron S. Wynn, Connie W. Cheung
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Patent number: 8839025Abstract: The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.Type: GrantFiled: September 30, 2011Date of Patent: September 16, 2014Assignee: Oracle International CorporationInventors: Ramaswamy Sivaramakrishnan, Ali Vahidsafa, Aaron S. Wynn, Connie W. Cheung
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Publication number: 20130086417Abstract: The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.Type: ApplicationFiled: September 30, 2011Publication date: April 4, 2013Inventors: Ramaswamy Sivaramakrishnan, Ali Vahidsafa, Aaron S. Wynn, Connie W. Cheung