Patents by Inventor Connie Wai Mun Cheung
Connie Wai Mun Cheung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9645903Abstract: A method for managing a failed memory module, including: receiving a first request to access a first memory address; identifying a memory module identifier (ID) from an end bit segment of the first memory address in the first request; generating, based on the memory module ID matching the failed memory module, a first revised memory address from the first memory address; and sending the first request with the first revised memory address to a memory controller for interpretation.Type: GrantFiled: March 31, 2015Date of Patent: May 9, 2017Assignee: Oracle International CorporationInventors: Ali Vahidsafa, Connie Wai Mun Cheung
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Patent number: 9569322Abstract: A method for memory migration between addressing schemes, including: receiving a first request to access a first memory address and a second request to access a second memory address; comparing the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un-migrated addresses; tagging the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending the first request to a first memory controller unit (MCU) and the second request to a second MCU.Type: GrantFiled: March 31, 2015Date of Patent: February 14, 2017Assignee: Oracle International CorporationInventors: Ali Vahidsafa, Connie Wai Mun Cheung
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Publication number: 20150278053Abstract: A method for managing a failed memory module, including: receiving a first request to access a first memory address; identifying a memory module identifier (ID) from an end bit segment of the first memory address in the first request; generating, based on the memory module ID matching the failed memory module, a first revised memory address from the first memory address; and sending the first request with the first revised memory address to a memory controller for interpretation.Type: ApplicationFiled: March 31, 2015Publication date: October 1, 2015Applicant: Oracle International CorporationInventors: Ali Vahidsafa, Connie Wai Mun Cheung
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Publication number: 20150278109Abstract: A method for memory migration between addressing schemes, including: receiving a first request to access a first memory address and a second request to access a second memory address; comparing the first memory address and the second memory address with a barrier pointer referencing a barrier address and separating migrated addresses and un-migrated addresses; tagging the first request with a first tag indicative of the first addressing scheme in response to the first memory address being on an un-migrated side of the barrier address; tagging the second request with a second tag indicative of the second addressing scheme in response to the second memory address being on a migrated side of the barrier address; and sending the first request to a first memory controller unit (MCU) and the second request to a second MCU.Type: ApplicationFiled: March 31, 2015Publication date: October 1, 2015Applicant: Oracle International CorporationInventors: Ali Vahidsafa, Connie Wai Mun Cheung
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Patent number: 8972663Abstract: A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave caches; receiving, by the RC and over the RN while the P2P request is pending, a forwarded request for the cacheline from a gateway; receiving, by the RC and after receiving the forwarded request, a plurality of responses to the P2P request from the plurality of slave caches; setting an intra-processor state of the cacheline in the RC, wherein the intra-processor state also specifies an inter-processor state of the cacheline; and issuing, by the RC, a response to the forwarded request after setting the intra-processor state and after the P2P request is complete; and modifying, by the RC, the intra-processor state in response to issuing the response to the forwarded request.Type: GrantFiled: March 14, 2013Date of Patent: March 3, 2015Assignee: Oracle International CorporationInventors: Paul N. Loewenstein, Stephen E. Phillips, David Richard Smentek, Connie Wai Mun Cheung, Serena Wing Yee Leung, Damien Walker, Ramaswamy Sivaramakrishnan
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Publication number: 20140281237Abstract: A method for cache coherence, including: broadcasting, by a requester cache (RC) over a partially-ordered request network (RN), a peer-to-peer (P2P) request for a cacheline to a plurality of slave caches; receiving, by the RC and over the RN while the P2P request is pending, a forwarded request for the cacheline from a gateway; receiving, by the RC and after receiving the forwarded request, a plurality of responses to the P2P request from the plurality of slave caches; setting an intra-processor state of the cacheline in the RC, wherein the intra-processor state also specifies an inter-processor state of the cacheline; and issuing, by the RC, a response to the forwarded request after setting the intra-processor state and after the P2P request is complete; and modifying, by the RC, the intra-processor state in response to issuing the response to the forwarded request.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Paul N. Loewenstein, Stephen E. Phillips, David Richard Smentek, Connie Wai Mun Cheung, Serena Wing Yee Leung, Damien Walker, Ramaswamy Sivaramakrishnan
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Patent number: 8549383Abstract: A cache memory system includes a cache controller and a cache tag array. The cache tag array includes one or more ways, one or more indices, and a cache tag entry for each way and index combination. Each cache tag entry includes an error correction portion and an address portion. In response to an address request for data that includes a first index and a first address, the cache controller compares the first address to the cache tag entries of the cache tag array that correspond to the first index. When the comparison results in a miss, the cache controller corrects cache tag entries with an error that correspond to the first index using the corresponding error correction portions, and stores at least one of the corrected cache tag entries in a storage that is external to the cache tag array. The cache controller, for each corrected cache tag entry, replays the comparison using the least one of the externally stored corrected cache tag entries.Type: GrantFiled: August 24, 2011Date of Patent: October 1, 2013Assignee: Oracle International CorporationInventors: Ramaswamy Sivaramakrishnan, Aaron S. Wynn, Connie Wai Mun Cheung, Satarupa Bose
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Patent number: 8527712Abstract: A method including: receiving multiple local requests to access the cache line; inserting, into an address chain, multiple entries corresponding to the multiple local requests; identifying a first entry at a head of the address chain; initiating, in response to identifying the first entry and in response to the first entry corresponding to a request to own the cache line, a traversal of the address chain; setting, during the traversal of the address chain, a state element identified in a second entry; receiving a foreign request to access the cache line; inserting, in response to setting the state element, a third entry corresponding to the foreign request into the address chain after the second entry; and relinquishing, in response to inserting the third entry after the second entry in the address chain, the cache line to a foreign thread after executing the multiple local requests.Type: GrantFiled: August 29, 2011Date of Patent: September 3, 2013Assignee: Oracle International CorporationInventors: Connie Wai Mun Cheung, Madhavi Kondapaneni, Joann Yin Lam, Ramaswamy Sivaramakrishnan
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Publication number: 20130055011Abstract: A cache memory system includes a cache controller and a cache tag array. The cache tag array includes one or more ways, one or more indices, and a cache tag entry for each way and index combination. Each cache tag entry includes an error correction portion and an address portion. In response to an address request for data that includes a first index and a first address, the cache controller compares the first address to the cache tag entries of the cache tag array that correspond to the first index. When the comparison results in a miss, the cache controller corrects cache tag entries with an error that correspond to the first index using the corresponding error correction portions, and stores at least one of the corrected cache tag entries in a storage that is external to the cache tag array. The cache controller, for each corrected cache tag entry, replays the comparison using the least one of the externally stored corrected cache tag entries.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Ramaswamy SIVARAMAKRISHNAN, Aaron S. WYNN, Connie Wai Mun CHEUNG, Satarupa BOSE
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Publication number: 20120290794Abstract: A method including: receiving multiple local requests to access the cache line; inserting, into an address chain, multiple entries corresponding to the multiple local requests; identifying a first entry at a head of the address chain; initiating, in response to identifying the first entry and in response to the first entry corresponding to a request to own the cache line, a traversal of the address chain; setting, during the traversal of the address chain, a state element identified in a second entry; receiving a foreign request to access the cache line; inserting, in response to setting the state element, a third entry corresponding to the foreign request into the address chain after the second entry; and relinquishing, in response to inserting the third entry after the second entry in the address chain, the cache line to a foreign thread after executing the multiple local requests.Type: ApplicationFiled: August 29, 2011Publication date: November 15, 2012Applicant: ORACLE INTERNATIONAL CORPORATIONInventors: Connie Wai Mun Cheung, Madhavi Kondapaneni, Joann Yin Lam, Ramaswamy Sivaramakrishnan