Patents by Inventor Connor Nace

Connor Nace has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Modular event-based performance monitoring in integrated circuit development
    Patent number: 11030370
    Abstract: Systems and methods to implement performance monitoring of a device under test involve defining one or more sequences. Each of the one or more sequences includes two or more events, each of the two or more events being defined by one or more hardware signals that include a hardware register value, transmission of a message or signal, or a wire voltage change. A method includes initiating a simulation of the device under test by inputting one or more signals at one or more inputs of the device under test for propagation across the device under test, and monitoring completion of the two or more events defining each of the one or more sequences. Performance of the device under test is reported. Reporting includes providing latency of each of the one or more sequences. A final design of the device under test is provided for fabrication based on the performance monitoring.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 8, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lahiruka Winter, Daniel Saconn, Kyle Phillips, Connor Nace, Zachary Neumann
  • MODULAR EVENT-BASED PERFORMANCE MONITORING IN INTEGRATED CIRCUIT DEVELOPMENT
    Publication number: 20210097146
    Abstract: Systems and methods to implement performance monitoring of a device under test involve defining one or more sequences. Each of the one or more sequences includes two or more events, each of the two or more events being defined by one or more hardware signals that include a hardware register value, transmission of a message or signal, or a wire voltage change. A method includes initiating a simulation of the device under test by inputting one or more signals at one or more inputs of the device under test for propagation across the device under test, and monitoring completion of the two or more events defining each of the one or more sequences. Performance of the device under test is reported. Reporting includes providing latency of each of the one or more sequences. A final design of the device under test is provided for fabrication based on the performance monitoring.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 1, 2021
    Inventors: Lahiruka Winter, Daniel Saconn, Kyle Phillips, Connor Nace, Zachary Neumann