Abstract: An IC device with one or more transistors may also include one or more vias and jumpers for delivering power to the transistors. For instance, a via may be coupled to a power plane. A jumper may be connected to the via and an electrode of a transistor. With the via and jumper, an electrical connection is built between the power plane and the electrode. The via may be self-aligned. The IC device may include a dielectric structure at a first side of the via. A portion of the jumper may be at a second side of the via. The second side opposes the first side. The dielectric structure and the portion of the jumper may be over another dielectric structure that has a different dielectric material from the dielectric structure. The via may be insulated from another electrode of the transistor, which may be coupled to a ground plane.

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more conductive vias is described herein. In one example, a conductive via is formed from one side of the integrated circuit, and then a portion of the conductive via is widened from a second side of the IC structure opposite the first side. In one example, a resulting IC structure includes a first portion having a first width, a second portion having a second width, and a third portion having a third width, wherein the third portion is between the first portion and the second portion, and the third width is smaller than the first width and the second width. In one such example, the conductive via tapers from both ends towards the third portion between the ends.

Abstract: A fabrication method and associated integrated circuit (IC) structures and devices that include one or more self-insulated vias is described herein. In one example, an IC structure includes a via surrounded by an insulator material and a layer of insulator material between a conductive material of the via and the surrounding insulator material. In one example, the layer of insulator material has one or more material properties that are different than the surrounding insulator material, including one or more of a different density, a different dielectric constant, and a different material composition.

Abstract: Integrated circuit structures having deep via bar width tuning are described. For example, an integrated circuit structure includes a plurality of gate lines extending over first and second semiconductor nanowire stack channel structures or fin structures. A plurality of trench contacts is intervening with the plurality of gate lines. A conductive structure is between the first and second semiconductor nanowire stack channel structures or fin structures, the conductive structure having a first width in a first region and a second width in a second region between the first and second semiconductor nanowire stack channel structures or fin structures, the second width different than the first width.

Abstract: An IC device may include one or more vias for delivering power to one or more transistors in the IC device. A via may have one or more widened ends to increase capacitance and decrease resistance. A transistor may include a source electrode over a source region and a drain electrode over a drain region. The source region or drain region may be in a support structure that has one or more semiconductor materials. The via has a body section and two end sections, the body section is between the end sections. One or both end sections are wider than the body section, e.g., by approximately 6 nanometers to approximately 12 nanometers. One end section is connected to an interconnect at the backside of the support structure. The other end section is connected to a jumper, which is connected to the source electrode or drain electrode.

Abstract: Techniques to form semiconductor devices can include one or more via structures having substrate taps. A semiconductor device includes a gate structure around or otherwise on a semiconductor region (or channel region). The gate structure may extend over the semiconductor regions of any number of devices along a given direction. The gate structure may be interrupted, for example, between two transistors with a via structure that extends through an entire thickness of the gate structure and includes a conductive core. The via structure has a conductive foot portion beneath the gate structure and a conductive arm portion extending from the conductive foot portion along a height of the gate structure. The conductive foot portion has a greater width along the given direction than any part of the conductive arm portion. The via structure may further include one or more dielectric layers between the conductive arm portion and the gate structure.

Abstract: Disclosed herein are IC structures and devices that aim to mitigate proximity effects of deep trench vias. An example IC structure may include a device region having a first face and a second face, the second face being opposite the first face, and further include a conductive via extending between the first face and the second face, wherein the conductive via includes an electrically conductive material, and wherein a concentration of titanium at sidewalls of the conductive via is below about 1015 atoms per cubic centimeter.

Abstract: Structures having a through-stack thermal sink for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure. The front side structure includes a device layer having a plurality of fin-based or nanowire-based transistors, and a plurality of metallization layers above the plurality of fin-based or nanowire-based transistors. A backside structure is below the plurality of fin-based or nanowire-based transistors. A carrier wafer or substrate is bonded to the front side structure. A thermal conductive via extends from a location at a bottom of or below the plurality of fin-based or nanowire-based transistors to a location on or into the carrier wafer or substrate.

Abstract: Integrated circuit structures having removed sub-fins, and methods of fabricating integrated circuit structures having removed sub-fins, are described. For example, an integrated circuit structure includes a channel structure, and a sub-fin isolation structure in a trench beneath the channel structure, wherein there is no residual silicon portion in the trench.

Abstract: Devices, transistor structures, systems, and techniques are described herein related to providing a backside passivation layer on a transistor semiconductor material. The semiconductor material is between source and drain structures, and a gate structure is adjacent a channel region of the semiconductor material. The passivation layer is formed as a conformal insulative layer on a backside of the semiconductor material and is then treated using an ozone/UV cure to remove trap charges from the semiconductor material.

Abstract: Integrated circuit structures having sub-fin isolation, and methods of fabricating integrated circuit structures having sub-fin isolation, are described. For example, an integrated circuit structure includes a channel structure, and an oxide sub-fin structure over the channel structure, the oxide sub-fin structure including silicon and oxygen and aluminum.

Abstract: An integrated circuit includes a first device, and a laterally adjacent second device. The first device includes a first body of semiconductor material extending laterally from a first source or drain region, a first gate structure on the first body, and a first contact extending vertically upward from the first source or drain region. The second device includes a second body of semiconductor material extending laterally from a second source or drain region, a second gate structure on the second body, and a second contact extending vertically upward from the second source or drain region. A gate cut structure including dielectric material is laterally between the first gate structure and the second gate structure, and also laterally between the first contact and the second contact. In some examples, a third contact extends laterally from the first contact to the second contact and passes over the gate cut structure.

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

Abstract: Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

Abstract: Embodiments disclosed herein include a via structure and methods of forming the via structure. In an embodiment, the via structure comprises a substrate and an opening through the substrate. In an embodiment, the opening has a first portion and a second portion under the first portion. In an embodiment, the via structure further comprises a lining on sidewalls of the first portion of the opening, and a via filling the opening. In an embodiment, the via has a first region with a first width and a second region with a second width, wherein the first width is smaller than the second width.

Abstract: Embodiments disclosed herein include a semiconductor device. In an embodiment, the semiconductor device comprises a substrate and a transistor over the substrate. In an embodiment, the transistor comprises a source, a gate, and a drain. In an embodiment, the semiconductor device further comprises a first metal layer above the transistor, where the first metal layer comprises, a source metal coupled to the source, a drain metal coupled to the drain, and a gate metal coupled to the gate. In an embodiment, the source metal, the drain metal, and the gate metal are parallel conductive lines. In an embodiment, a backside via passes through the substrate, and a contact metal in the first metal layer is coupled to the backside via. In an embodiment, the contact metal is oriented orthogonal to the source metal.

Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.

Abstract: Integrated circuit structures having backside power delivery are described. In an example, an integrated circuit structure includes a device layer within a cell boundary, the device layer having a front side and a backside, and the device layer including a source or drain structure. A source or drain trench contact structure is on the front side of the device layer. The source or drain trench contact structure is coupled to the source or drain structure. A metal layer is on the backside of the device layer. A via structure couples the metal layer to the source or drain trench contact structure. The via structure is overlapping and parallel with a cell row boundary of the cell boundary.

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for providing a hermetic seal for a layer of transistors with metal on both sides that are on a substrate. The layer of transistors may be within a die or within a portion of a die. The hermetic seal may include a hermetic layer on one side of the layer of transistors and a hermetic layer on the opposite side of the transistors. In embodiments, one or more metal walls may be constructed through the transistor layer, with metal rings placed around either side of the layer of transistors and hermetically coupling with the two hermetic layers. Other embodiments may be described and/or claimed.