Patents by Inventor Conor Puls

Conor Puls has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Backside processing of fins in fin based transistor devices
    Patent number: 12543367
    Abstract: An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: February 3, 2026
    Assignee: INTEL CORPORATION
    Inventors: Tao Chu, Minwoo Jang, Aurelia Chi Wang, Conor Puls, Brian Greene, Tofizur Rahman, Lin Hu, Jaladhi Mehta, Chung-Hsun Lin, Walid Hafez
  • BACKSIDE PROCESSING OF FINS IN FIN BASED TRANSISTOR DEVICES
    Publication number: 20230307449
    Abstract: An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).
    Type: Application
    Filed: March 25, 2022
    Publication date: September 28, 2023
    Applicant: Intel Corporation
    Inventors: Tao Chu, Minwoo Jang, Aurelia Chi Wang, Conor Puls, Brian Greene, Tofizur Rahman, Lin Hu, Jaladhi Mehta, Chung-Hsun Lin, Walid Hafez
  • Magnetic memory devices with layered electrodes and methods of fabrication
    Patent number: 11380838
    Abstract: A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Justin Brockman, Conor Puls, Stephen Wu, Christopher Wiegand, Tofizur Rahman, Daniel Ouellette, Angeline Smith, Andrew Smith, Pedro Quintero, Juan Alzate-Vinasco, Oleg Golonzka
  • MAGNETIC MEMORY DEVICES WITH LAYERED ELECTRODES AND METHODS OF FABRICATION
    Publication number: 20200006634
    Abstract: A memory device method of fabrication that includes a first electrode having a first conductive layer including titanium and nitrogen and a second conductive layer on the first conductive layer that includes tantalum and nitrogen. The memory device further includes a magnetic tunnel junction (MTJ) on the first electrode. In some embodiments, at least a portion of the first conductive layer proximal to an interface with the second conductive layer includes oxygen.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: Justin Brockman, Conor Puls, Stephen Wu, Christopher Wiegand, Tofizur Rahman, Daniel Ouellette, Angeline Smith, Andrew Smith, Pedro Quintero, Juan Alzate-Vinasco, Oleg Golonzka