Patents by Inventor Conrad Barile
Conrad Barile has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8053257Abstract: The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for a layer within chips comprising a semiconductor wafer lot. If only one mode is calculated, that is the best calculated mode. If multiple modes can be calculated, a best mode that most accurately represents dielectric breakdown for the semiconductor wafer lot is determined. Premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation from the best calculated mode.Type: GrantFiled: April 2, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Kaushik Chanda, Hazara S. Rathore, Paul S. McLaughlin, Robert D. Edwards, Lawrence A. Clevenger, Andrew P. Cowley, Chih-Chao Yang, Conrad A. Barile
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Publication number: 20080174334Abstract: The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of breakdown voltages within said calculated mode. If multiple modes are calculated, the mode that most accurately represents dielectric breakdown for the semiconductor wafer is determined and premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard of the calculated mode that most accurately represents dielectric breakdown for the semiconductor wafer.Type: ApplicationFiled: April 2, 2008Publication date: July 24, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kaushik Chanda, Hazara S. Rathore, Paul S. McLaughlin, Robert D. Edwards, Lawrence A. Clevenger, Andrew P. Cowley, Chih-Chao Yang, Conrad A. Barile
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Publication number: 20060281338Abstract: The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of breakdown voltages within said calculated mode. If multiple modes are calculated, the mode that most accurately represents dielectric breakdown for the semiconductor wafer is determined and premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard of the calculated mode that most accurately represents dielectric breakdown for the semiconductor wafer.Type: ApplicationFiled: June 14, 2005Publication date: December 14, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kaushik Chanda, Hazara Rathore, Paul McLaughlin, Robert Edwards, Lawrence Clevenger, Andrew Cowley, Chih-Chao Yang, Conrad Barile
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Patent number: 7138714Abstract: The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure.Type: GrantFiled: February 11, 2005Date of Patent: November 21, 2006Assignee: International Business Machines CorporationInventors: Du B. Nguyen, Birendra N. Agarwala, Conrad A Barile, Jawahar P. Nayak, Hazara S. Rathore
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Publication number: 20060180930Abstract: The present invention provides an interconnect structure that includes a diffusion barrier which is positioned within the structure in a fashion that increases the reliability and lifetime of the interconnect structure.Type: ApplicationFiled: February 11, 2005Publication date: August 17, 2006Applicant: International Business Machines CorporationInventors: Du Nguyen, Birendra Agarwala, Conrad Barile, Jawahar Nayak, Hazara Rathore
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Publication number: 20060014376Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.Type: ApplicationFiled: September 20, 2005Publication date: January 19, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Birendra Agarwala, Conrad Barile, Hormazdyar Dalal, Brett Engel, Michael Lane, Ernest Levine, Xiao Liu, Vincent McGahay, John McGrath, Conal Murray, Jawahar Nayak, Du Nguyen, Hazara Rathore, Thomas Shaw
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Patent number: 6972209Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.Type: GrantFiled: November 27, 2002Date of Patent: December 6, 2005Assignee: International Business Machines CorporationInventors: Birendra N. Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engle, Michael Lane, Ernest Levine, Xiao Hu Liu, Vincent McGahay, John F. McGrath, Conal E. Murray, Jawahar P. Nayak, Du B. Nguyen, Hazara S. Rathore, Thomas M. Shaw
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Publication number: 20040101663Abstract: A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material.Type: ApplicationFiled: November 27, 2002Publication date: May 27, 2004Inventors: Birendra N. Agarwala, Conrad A. Barile, Hormazdyar M. Dalal, Brett H. Engel, Michael Lane, Ernest Levine, Xiao Hu Liu, Vincent McGahay, John F. McGrath, Conal E. Murray, Jawahar P. Nayak, Du B. Nguyen, Hazara S. Rathore, Thomas M. Shaw
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Patent number: 4243435Abstract: A very high current ion implanted emitter is formed in a diffused base. Windows are made through the silicon nitride and silicon dioxide layes to both the base contact and the emitter regions using a resist mask. These regions are then protected by resist and the collector contact window is opened through the remainder of the silicon dioxide layer to the reach through region. A screen oxide is then grown in all the exposed areas after the removal of the resist mask. A resist mask is applied which covers only the base and Schottky anode regions. Arsenic is then implanted through the exposed screened areas followed by an etch back step to remove the top damaged layer. With some remaining screen oxide serving as a cap, the emitter drive-in is done.Type: GrantFiled: June 22, 1979Date of Patent: January 6, 1981Assignee: International Business Machines CorporationInventors: Conrad A. Barile, Goerge R. Goth, James S. Makris, Arunachala Nagarajan, Raj K. Raheja
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Patent number: 4060427Abstract: A region in an integrated circuit substrate is formed by first ion implanting impurities of a selected conductivity-determining type into a semiconductor substrate through at least one aperture in a masking electrically insulative layer, and then diffusing a conductivity-determining impurity of the same type through the same aperture into said substrate.The method has particular application when the electrically insulative layer is a composite of two layers, e.g., a top layer of silicon nitride and a bottom layer of silicon dioxide and the aperture is thus a pair of registered openings respectively through said silicon nitride and silicon dioxide layers, and the aperture through the silicon dioxide layer has greater lateral dimensions than that in the silicon nitride layer to provide an undercut beneath the silicon nitride ion implantation barrier layer.Type: GrantFiled: April 5, 1976Date of Patent: November 29, 1977Assignee: IBM CorporationInventors: Conrad A. Barile, Robert M. Brill, John L. Forneris, Joseph Regh