Abstract: A method of processing an input image includes receiving an input signal associated with the input image. The input signal includes a plurality of components. The method also includes determining a minimum component of the plurality of components and determining a white signal level as a function of the minimum component. The method further includes multiplying the white signal level by a normalized value computed using a component of the plurality of components to provide a scaled white signal level.

Abstract: A vector-domain engine configured to perform conditional operations on an operand vector in a programmable logic device is disclosed. The vector-domain engine may receive an instruction from and transmit an output vector to a programmable-logic-device domain. The output vector may be a first or second output vector depending on whether a comparison unit in the engine determines that a bit-field of the operand vector matches a designated pattern. The first output vector may be the operand vector modified by a function unit, and the second output vector may be the operand vector unmodified. A shifter may be employed to shift the bit-field to a desired position in the operand vector. The operand vector may comprise a pattern-defining portion and a data portion. The engine may also be configured to test a predetermined number of sequential operand vectors for the presence of the pattern.

Abstract: A method is disclosed to efficiently route in a programmable logic device (PLD) such as a field-programmable gate array (FPGA). The method includes identifying a source and destination pair in a circuit design; determining multiple candidate paths to route a vector between the source and destination pair; and selecting one of the candidate paths for the vector route. Efficiency may be improved by using time-division multiplexing to route multiple connections through a PLD element.

Abstract: A circuit is disclosed for a programmable logic device (PLD) environment that converts unordered bits in a PLD domain to fixed-width vectors in a vector domain. The fixed-width vectors may be used within a vector processing block (VPB) that operates on data in vector format. The PLD includes multiple programmable logic blocks that are configurable by a user. The logic blocks operate on data at a bit level resulting in unordered bits of information in a PLD domain. However, a vector processing block operates on data on a vector level (e.g., 8 bits, 16 bits, 32 bits, 64 bits, etc.). Thus, an interface is coupled between the programmable logic blocks and the vector processing block that converts at least a portion of the unordered bits of information from the PLD domain to one or more fixed-width vectors for use in the vector processing block. The interface may also perform scaling and/or sign extension on the unordered bits, to further free up expensive resources in the PLD domain.

Abstract: A PLD is disclosed that uses vector routing between components. A vector routing path is coupled between the components and includes a group of wires for routing a group of bits as one vector so that all bits in the vector are switched at once and as a group by a single set of control signals. Vector switch boxes are used to switch entire vectors of a predetermined bit width and a fixed-bit order. The vector routing may be between components in a vector domain, within vector-based components, or between components in a PLD domain and a vector domain. The vector routing path may allow for time-division multiplexing. For example, different components may use the same vector routing path during different time slices. The vector routing path may be dynamically segmented. Dynamic segmentation allows different portions of the same vector routing path to be used simultaneously by different components. A component may be coupled to multiple vector routing paths through a multiplexer.

Abstract: A circuit is disclosed for a programmable logic device (PLD) environment that converts unordered bits in a PLD domain to fixed-width vectors in a vector domain. The fixed-width vectors may be used within a vector processing block (VPB) that operates on data in vector format. The PLD includes multiple programmable logic blocks that are configurable by a user. The logic blocks operate on data at a bit level resulting in unordered bits of information in a PLD domain. However, a vector processing block operates on data on a vector level (e.g., 8 bits, 16 bits, 32 bits, 64 bits, etc.). Thus, an interface is coupled between the programmable logic blocks and the vector processing block that converts at least a portion of the unordered bits of information from the PLD domain to one or more fixed-width vectors for use in the vector processing block. The interface may also perform scaling and/or sign extension on the unordered bits, to further free up expensive resources in the PLD domain.