Abstract: A system and method for dithering a clock signal during idle times is disclosed. An integrated circuit (IC) includes a number of functional units and a clock tree. The clock tree includes a root level clock-gating circuit, a number of regional clock-gating circuits, and a number of leaf level clock-gating circuits. The root level clock-gating circuit is coupled to distribute an operating clock signal to the regional clock-gating circuits, while the regional clock-gating circuits are each configured to distribute the operating clock signal to correspondingly coupled ones of the leaf level clock-gating circuits. The IC may further include a control unit configured to monitor activity levels and indications from each of the functional units. The control unit may cause the root clock-gating circuit to dither the clock signal if the IC is idle, wherein dithering includes reducing the duty cycle and the effective frequency of the operating clock signal.

Abstract: In an embodiment, an integrated circuit includes a power gated block and a power manager circuit. The power manager circuit is configured to provide a block enable signal and at least one select signal to the power gated block. The power manager may generate the select signal responsive to various parameters that affect the speed of the integrated circuit, such as power supply voltage magnitude, operating temperature, and/or process corner. The power gated block may control the rate at which power switches are enabled based on the select signal or signals. For example, the power switches may be enabled in a more parallel or more serial fashion and/or the drive strength of block enable buffering to the power switches may be varied. In another embodiment, the power manager circuit may assert multiple block enables to the power gated block (which are connected to separate sets of power switches), and may control the timing of assertion of the enables to control the rate at which power switches are enabled.

Abstract: A system, apparatus, and method for writing trace data to storage. Trace data is captured from one or more processors, and then the trace data is written to a trace buffer. The trace data includes program counters of instructions executed by the processors and other debug data. A direct memory access (DMA) controller in a non-real-time block of the system reads trace data from the trace buffer and then writes the trace data to memory via a non-real-time port of a memory controller.

Abstract: A system and method for efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC). A SOC includes an interrupt controller and multiple processing cores. The interrupt controller includes a main time base counter. The SOC includes multiple local time base counters, each coupled to a respective one of the processing cores. Synchronization logic blocks are used to update the local counters. These blocks receive a subset of bits from the interrupt controller. The subset of bits represents a number of least significant bits of the main counter less than a total number of bits for the main counter. The logic blocks update an associated local counter according to changes to the received subset of bits. A difference may exist between values of the main counter in the interrupt controller and the local counter in the processing core. However, this difference may be a constant value.

Abstract: In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.

Abstract: A memory may include a memory array, a plurality of control circuits, and a plurality of isolation circuits. The plurality of control circuits may be configured to generate control signals for the memory array. For example, the plurality of control circuits may include a plurality of word line driver circuits. The plurality of isolation circuits may be configured to receive the control signals from the plurality of control circuits and a plurality of isolation signals. A first isolation signal may correspond to the plurality of word line driver circuits and at least one second isolation signal may correspond to other ones of the plurality of control circuits. The first isolation signal and the second isolation signal may be independently controlled during memory tests to detect stuck-at faults associated with the plurality of isolation signals.

Abstract: In an embodiment, an integrated circuit comprises a plurality of temperature sensors and a power manager coupled thereto. The temperature sensors are physically distributed over an area of the integrated circuit that is occupied by logic circuitry implementing the operations for which the integrated circuit is designed. The power manager is configured to transmit a power supply voltage request to an external power supply module, the power supply voltage request indicating a requested magnitude of the power supply voltage for the integrated circuit. The power manager is configured to modify the requested magnitude responsive to indications from each of the plurality of temperatures sensors that represent a temperature of the integrated circuit sensed by each of the plurality of temperature sensors.

Abstract: In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.

Abstract: In an embodiment, an integrated circuit includes a power gated block and a power manager circuit. The power manager circuit is configured to provide a block enable signal and at least one select signal to the power gated block. The power manager may generate the select signal responsive to various parameters that affect the speed of the integrated circuit, such as power supply voltage magnitude, operating temperature, and/or process corner. The power gated block may control the rate at which power switches are enabled based on the select signal or signals. For example, the power switches may be enabled in a more parallel or more serial fashion and/or the drive strength of block enable buffering to the power switches may be varied. In another embodiment, the power manager circuit may assert multiple block enables to the power gated block (which are connected to separate sets of power switches), and may control the timing of assertion of the enables to control the rate at which power switches are enabled.

Abstract: In an embodiment, an integrated circuit comprises a plurality of temperature sensors and a power manager coupled thereto. The temperature sensors are physically distributed over an area of the integrated circuit that is occupied by logic circuitry implementing the operations for which the integrated circuit is designed. The power manager is configured to transmit a power supply voltage request to an external power supply module, the power supply voltage request indicating a requested magnitude of the power supply voltage for the integrated circuit. The power manager is configured to modify the requested magnitude responsive to indications from each of the plurality of temperatures sensors that represent a temperature of the integrated circuit sensed by each of the plurality of temperature sensors.

Abstract: In an embodiment, an integrated circuit comprises a decompressor, an encrypt unit, and an on-chip image buffer coupled to the decompressor and the encrypt unit. The decompressor is configured to receive a compressed video stream, and to reconstruct a first frame of the video stream in the on-chip buffer. The encrypt unit is configured to generate one or more pixel block streams from pixel blocks of the first frame in the on-chip buffer according to sequence data describing an order of access of the pixel blocks to reconstruct subsequent frames of the video stream. The sequence data was previously generated via processing of the video stream by the integrated circuit, and the encrypt unit is configured to encrypt the pixel block streams to be written to an external memory. In an embodiment, an integrated circuit comprises a decrypt unit configured to decrypt an encrypted, compressed video stream; an on-chip buffer; and a decompressor coupled to the decrypt unit and the on-chip buffer.

Abstract: Disclosed herein are digital systems and methods for use with a ramped clock signal. The digital system includes an input element having a data input to receive a data signal, a control input to receive a control signal, and a dynamic node to be driven by the ramped clock signal. The digital system further includes a static memory element having an input at the dynamic node and is configured to reside in an operational state in accordance with the data signal and the ramped clock signal. The input element further includes a switch coupled to the control input to condition updating of the operational state based on the control signal without decoupling the ramped clock signal from the dynamic node. In this way, distribution and delivery of the ramped clock signal to the digital system is continued to facilitate recovery of clock signal energy from the digital system.

Abstract: A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected between at least two of the plurality of transistors wherein the plurality of transistors are configured to generate a second voltage from a first voltage at the electrical node in response to the clock signal.

Abstract: A flip-flop includes a charge storage area that stores a logic voltage indicating a logic state of the flip-flop, a first transistor having a source or drain connected to a clock signal generating circuit, a second transistor having a source or drain connected to the clock signal generating circuit, a clock signal generated by the clock signal generating circuit that is ramped or sinusoidal, and a latching circuit that latches a latch voltage value based on voltages at the first transistor and the second transistor. The charge storage area supplies a first voltage representing a state of the storage voltage to a gate of the first transistor and supplies a second voltage to a gate of the second transistor.

Abstract: A clock signal generating circuit includes an oscillator portion that sustains a ramped oscillating clock signal in a memory storage device electrically connected to the oscillator portion, a switch portion that supplements electrical energy to the oscillator portion, and a cycle controller connected to the oscillator portion and the switch portion to supplement energy to the oscillator portion when a peak voltage or current level of the clock signal falls below a predetermined value.

Abstract: A flip-flop includes a charge storage area that stores a logic voltage indicating a logic state of the flip-flop, a first transistor having a source or drain connected to a clock signal generating circuit, a second transistor having a source or drain connected to the clock signal generating circuit, a clock signal generated by the clock signal generating circuit that is ramped or sinusoidal, and a latching circuit that latches a latch voltage value based on voltages at the first transistor and the second transistor. The charge storage area supplies a first voltage representing a state of the storage voltage to a gate of the first transistor and supplies a second voltage to a gate of the second transistor.