Abstract: A circuit arrangement including means for determining a slicer level from incoming signal levels for slicing the incoming signal levels on the basis of the slicer level thus determined, includes a first and a second register circuit, which register circuits are connected to an output of a discriminator circuit. The discriminator circuit compares an incoming signal level with a set discrimination level and is adapted to apply an incoming signal level to the first register circuit if the incoming signal level is higher than the set discrimination level and to apply and incoming signal level to the second register circuit if the incoming signal level is lower than the set termination level. The first and the second register circuit are adapted to determine a register value of a least two different incoming signal levels consecutively applied to the register circuit. The circuit supplies a signal having a level which is a value determine from register values determined by the first and second register circuit.

Abstract: A record carrier is described that has a servo track (4) indicating an information track (9) intended for recording information blocks. The servo track (4) has a periodic variation of a physical parameter at a predetermined frequency and modulated parts for encoding position information at regular intervals. The modulated parts start with a bit sync element and are of a data type having a data bit element or of a word sync type having a word sync element. The bit sync element, word sync element and the data bit element being modulated according to a same predetermined type of modulation of the periodic variation. The distances between all elements constituting the modulated parts are unique. Further a device for reading and/or writing the record carrier is described.

Abstract: The invention relates to method of encoding address words (a) comprising address symbols (a0, a1, . . . , ak−1) into codewords (c) of a code (C) for providing an enhanced error correction capability if at least one information symbol (m1) of information words (m) is known a priori to a decoder decoding received, possibly mutilated codewords (r). The invention relates further to a method of decoding possibly mutilated codewords (r).

Abstract: In a transmission system for digital symbols, such as used for DVB, source symbols are encoded by a block coder (4), subjected to an interleaving operation in an interleaver and subsequently encoder in a channel encoder (8) according to one out of a plurality of possible channel codes. The output symbols of the channel encoder (8) are applied to transmit means (10). These output symbols are modulated on a carrier and applied to an antenna (12). An antenna (14) connected to a receiver (16) receives the signal transmitted by the antenna (12). Receive means (18) are arranged for amplifying and demodulating the signal received from the antenna (14). The output of the receive means (18) are applied to quantizing means (20) which convert its input signal into a quantized digital signal, before applying it to a Viterbi decoder 22. The complexity of the Viterbi decoder 22 depends on the number of quantization levels at the output of the quantization means (20).

Abstract: The invention relates to a method of selecting a generator matrix (G) for encoding information words (m) comprising information symbols (m1, m2, . . . , mk) into codewords (c) of a code (C) for providing an enhanced error correction capability if at least one information symbol (m1, m2, m3) is known a priori to a decoder decoding received, possibly mutilated codewords (r). The invention relates further to a method of encoding information words (m) into codewords (c) and to a method of decoding possibly mutilated codewords (r).

Abstract: A system (70) comprising a microprocessor (74), a data bus (75) for writing data into a Flash memory device (71) and a data bus (75) for reading data from the Flash memory device (71). The Flash memory device (71) comprises an error correction encoder (72), a Flash memory (71), an error correction decoder (73), and a Flash data bus (75) for interconnecting the error correction encoder (72), the Flash memory (71), and the error correction decoder (73). The data, when being processed by the error correction encoder (72) are converted into a word that comprises a status word (51), a data word (52), and a redundancy word (53). This approach enables error correction with single-bit alterability.

Abstract: Hashes are short summaries or signatures of data files which can be used to identify the file. Hashing multimedia content (audio, video, images) is difficult because the hash of original content and processed (e.g. compressed) content may differ significantly.

Abstract: The invention relates to a method and device for encoding information words and a method and device for decoding as well as a storage medium for storing and a signal comprising such encoded information words. In order to improve the properties of a burst-indicator subcode it is proposed to encode the bits of a burst-indicator subcode byte into different channel words. Thus, these bits are spread over an entire frame of encoded data improving burst error detecting and correcting properties.

Abstract: The invention relates to a method for generating a serial bitstream comprising information for synchronizing the serial bitstream internally and/or to another serial bitstream and/or for determining the position in the serial bitstream wherein a fixed code pattern is embedded in the serial bitstream. In order to retrieve a synchronization information or to determine the position in the serial bitstream very fast after the start of reading the serial bitstream and at any time during reading the serial bitstream it is provided according to the invention that the code pattern is periodically repeated in the serial bitstream and that any sequence of a fixed number of successive bits of the code pattern forms a unique code word allowing for synchronization and/or position determination, even under the occurrence of bit errors.

Abstract: A communication system (1) comprises a transmitter (2), a receiver (3), and an up/down link communication channel (4, 6) arranged for data communication from the transmitter (2) through the up link communication channel (4) to the receiver (3). The communication system (1) is further arranged to feedback data from the receiver (3) through the down link communication channel (6) to the transmitter (2). The receiver (3) comprises a bad frame indicator (5) for providing a bad frame indication (BFI) upon receipt of a corrupted frame, which is present in synchronized data communicated over the up link communication channel (4); and the transmitter (2) comprises resynchronization means (7) coupled to the down link communication channel (6) for receiving BFI related data and in response thereto recommencing data communication over the up link communication channel (4), in accordance with a resynchronization procedure, which starts from a predetermined state.

Abstract: The invention relates to a method of storing a number of data bits of a secondary channel (30) in the frame of a main channel (20) and to a method of decoding a stream of bits relating to a secondary channel (30) embedded in the frames of a main channel (20) into a stream of data bits (62). In order to enable a certain synchronization and to guarantee a fixed amount of storage capacity in the secondary channel as well as to be able to correct deletions or insertions of bits in the secondary channel it is proposed according to the invention to form a secondary frame (11) having a fixed number of frame bits, to fill a fixed part of the secondary frame (11) with data bits (113), an end-bit (114) set to a first bit-value and, if necessary, with filling bits (115) set to a second bit-value, to encode the secondary frame (11) producing encoded data bits (113) and parity bits (112), which are finally embedded in the frame of the main channel (20).

Abstract: A circuit arrangement including means (5) for determining a slicer level from incoming signal levels for slicing the incoming signal levels on the basis of the slicer level thus determined, includes a first (15, 21, 131, 43) and a second (16, 22, 132, 44) register circuit, which register circuits are connected to an output (11, 12) of a discriminator circuit (8). The discriminator circuit (8) compares an incoming signal level with a set discrimination level and is adapted to apply an incoming signal level to the first register circuit (15, 21, 131, 43) if the incoming signal level is higher than the set discrimination level and to apply an incoming signal level to the second register circuit (16, 22, 132, 44) if the incoming signal level is lower than the set discrimination level.