Abstract: An asymmetric insulated-gate field-effect transistor (40) is configured in an asymmetric lightly doped drain structure that alleviates hot-carrier effects and enables the source characteristics to be decoupled from the drain characteristics. The transistor has a multi-part channel formed with an output portion (46), which adjoins the drain zone, and a more heavily doped input portion (42), which adjoins the source zone (44). The drain zone contains a main portion (52) and a more lightly doped extension (50) that meets the output channel portion. The drain extension extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion is situated in a threshold body zone (53) whose doping determines the threshold voltage. The provision of a lightly doped source extension is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa.

Abstract: To furnish an IGFET (120 or 122) with an asymmetrically doped channel zone (144 or 164), a mask (212) is provided over a semiconductor body and an overlying electrically insulated gate electrode (148P or 168P). Ions of a semiconductor dopant species are directed toward an opening (213) in the mask from two different angular orientations along paths that originate laterally beyond opposite respective opening-defined sides of the mask. The location and shape of the opening are controlled so that largely only ions impinging from one of the angular orientations enter the intended location for the channel zone. Ions impinging from the other angular orientation are shadowed by the mask from entering the channel zone location. Although the ions impinging from this other angular orientation do not significantly dope the channel zone location, they normally enter the semiconductor body elsewhere, e.g., the intended location for the channel zone of another IGFET.

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.

Abstract: A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance.

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.1 &mgr;m deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

Abstract: An insulated-gate field-effect transistor utilizes local threshold-adjust doping to control the voltage at which the transistor turns on. The local threshold-adjust doping is present along part, but not all, of the lateral extent of the channel. In the transistor structure, a channel zone laterally separates a pair of source/drain zones. The channel zone is formed with a main channel portion and a more heavily doped threshold channel portion that contains the local threshold-adjust doping. Gate dielectric material vertically separates the channel zone from an overlying gate electrode. The transistor is a long device in that the gate electrode is longer, preferably at least 50% longer, than the gate electrode of a minimum-sized transistor whose gate length is approximately the minimum feature size. The long-gate transistor is suitable for use in analog and high-voltage digital portions of a VLSI circuit.

Abstract: An asymmetric insulated-gate field-effect transistor is configured in an asymmetric lightly doped drain structure that alleviates hot-carrier effects and enables the source characteristics to be decoupled from the drain characteristics. The transistor has a multi-part channel formed with an output portion, which adjoins the drain zone, and a more heavily doped input portion, which adjoins the source zone. The drain zone contains a main portion and more lightly doped extension that meets the output channel portion. The drain extension extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion is situated in a threshold body zone whose doping determines the threshold voltage. Importantly, the provision of a lightly doped source extension is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa.

Abstract: A structure containing multiple field-effect transistors (60 and 150) is fabricated from a semiconductor body having material (82) of a specified conductivity type. Semiconductor dopant of the specified conductivity type is introduced, typically simultaneously, (a) into part of a first channel zone of the material of the specified conductivity type to define a threshold channel portion (66) more heavily doped than a main channel portion (65) and (b) into substantially all of a second channel zone of the material of the specified conductivity type. First and second gate electrodes (69 and 141) are provided respectively above, and insulatingly spaced apart from, the first and second channel zones.

Abstract: A pair of complementary CJIGFETs (100 and 160) are created from a body of semiconductor material (102 and 104). Each CJIGFET is formed with (a) a pair of laterally separated source/drain zones (112 and 114 or 172 and 174) situated along the upper surface of the semiconductor body, (b) a channel region (110 or 170) extending between the source/drain zones, and (c) a gate electrode (118 or 178) overlying, and electrically insulated from, the channel region. The gate electrode of each CJIGFET has a Fermi energy level within 0.3 ev of the middle of the energy band gap of the semiconductor material. One of the transistors typically conducts current according to a field-induced-channel mode while the other transistor conducts current according to a metallurgical-channel mode. The magnitude of the threshold voltage for each CJIGFET is normally no more than 0.5 V.

Abstract: An insulated gate field effect transistor is manufactured according to a process in which an insulated gate structure is formed along a semiconductor chip. Dopant is introduced into the chip to form a body region, semiconductor material outside the body region forming a drain region. Dopant is introduced into the chip at the location of part of the body region to form a source region spaced apart from the drain region by a channel region. Dopant of the same conductivity type as the body-region dopant is introduced through a dopant-introducing section of the chip's upper surface and into the chip at the location of part of the body region to form a sub-surface peaked portion of the body region, the dopant-introducing section being spaced laterally apart from the channel and source regions. The sub-surface peaked portion reaches a peak net dopant concentration below the chip's upper surface so as to improve the transistor's ruggedness under drain avalanche conditions.

Abstract: Two topologically different cells are disclosed that reduce the total number of contacts per device and that are applicable to mid- to high-voltage DMOS transistors. These cells use integrated connections between the source and the body that make them less sensitive to contact obturations by particle contamination or lithography imperfections. The topologies include either an elongated hexagonal cell or a buried-deep-body cell. Both cells are most efficient in high-current medium-voltage trench DMOS transistors, where the density of body contacts becomes prohibitive while the perimeter/area geometry factor is less critical. The disclosed embodiments are of the trench type of DMOS construction. The cells may, however, be implemented in planar DMOS transistors as well.

Abstract: Each of a pair of complementary insulated-gate field-effect transistors is manufactured in an asymmetric lightly doped drain structure that enables the source characteristics to be decoupled from the drain characteristics. Each transistor has a multi-part channel formed with an output portion, which adjoins the drain zone, and a more heavily doped input portion, which adjoins the source zone. The drain zone of each transistor contains a main portion and a more lightly doped extension that meets the output channel portion. The drain extension of each transistor typically extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion of each transistor is situated in a threshold body zone whose doping determines the threshold voltage. Importantly, the provision of lightly doped source extensions is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa.

Abstract: An insulated gate semiconductor device contains a common drain and a plurality of cells, each having a body region and a source. In each cell, the body region contains a channel region extending between the common drain and the source. The body region further includes a special portion spaced apart from the channel region, more heavily doped than the portion of the body region below the source, extending no more than an electrically insignificant amount below the source, and not extending significantly deeper below the upper semiconductor surface than the portion of the body region underlying the source. The special portion of each body region provides improved ruggedness under drain avalanche conditions. The special portion of each body region normally reaches a peak net dopant concentration below the upper semiconductor surface.

Abstract: Parts of the emitter and base of a vertical bipolar transistor adjoin a field-isolation region to form a walled-emitter structure. The transistor is furnished with extra doping in the collector and, optionally, in the base. The extra collector doping is provided along collector-base junction below the intrinsic base to create a special collector zone spaced laterally apart from the field-isolation region. The presence of the special collector zone causes the intrinsic base to be thinner, thereby raising the cutoff frequency and overall current gain. The extra base doping is provided in the intrinsic base along the field-isolation region to improve the transistor's breakdown voltage and leakage current characteristics.

Abstract: A special two-dimensional intrinsic base doping profile is utilized to improve the output current-voltage characteristics of a vertical bipolar transistor whose intrinsic base includes a main intrinsic portion. The special doping profile is achieved with a pair of more lightly doped base portions that encroach substantially into the intrinsic base below the main intrinsic base portion. The two deep encroaching base portions extend sufficiently close to each other to set up a two-dimensional charge-sharing mechanism that typically raises the magnitude of the punch-through voltage. The transistor's current-voltage characteristics are thereby enhanced. Manufacture of the transistor entails introducing suitable dopants into a semiconductor body. In one fabrication process, a fast-diffusing dopant is employed in forming the deep encroaching base portions without significantly affecting earlier-created transistor regions.

Abstract: Parts of the emitter and base of a vertical bipolar transistor adjoin a field-isolation region to form a walled-emitter structure. The transistor is furnished with extra doping in the collector and, optionally, in the base. The extra collector doping is provided along collector-base junction below the intrinsic base to create a special collector zone spaced laterally apart from the field-isolation region. The presence of the special collector zone causes the intrinsic base to be thinner, thereby raising the cutoff frequency and overall current gain. The extra base doping is provided in the intrinsic base along the field-isolation region to improve the transistor's breakdown voltage and leakage current characteristics.

Abstract: A special two-dimensional intrinsic base doping profile is utilized to improve the output current-voltage characteristics of a vertical bipolar transistor whose intrinsic base includes a main intrinsic portion. The special doping profile is achieved with a pair of more lightly doped base portions that encroach substantially into the intrinsic base below the main intrinsic base portion. The two deep encroaching base portions extend sufficiently close to each other to set up a two-dimensional charge-sharing mechanism that typically raises the magnitude of the punch-through voltage. The transistor's current-voltage characteristics are thereby enhanced.

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract: Two topologically different cells are disclosed that reduce the total number of contacts per device and that are applicable to mid- to high-voltage DMOS transistors. These cells use integrated connections between the source and the body that make them less sensitive to contact obturations by particle contamination or lithography imperfections. The topologies include either an elongated hexagonal cell or a buried-deep-body cell. Both cells are most efficient in high-current medium-voltage trench DMOS transistors, where the density of body contacts becomes prohibitive while the perimeter/area geometry factor is less critical. The disclosed embodiments are of the trench type of DMOS construction. The cells may, however, be implemented in planar DMOS transistors as well.

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior Which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.