Abstract: Disclosed is a technique for updating a read-detect channel. A signal is processed in a read-detect channel that has one or more programmable registers. While signals continue to be processed by the read-detect channel, it is determined with a channel auxiliary processor whether to dynamically replace values of the one or more programmable registers. When it is determined that values of the one or more programmable registers are to be replaced, a channel auxiliary processor determines values for the one or more programmable registers and replaces existing values for the one or more programmable registers with the determined values.

Abstract: Provided is a method, system, and program for providing synchronization in a binary data stream. A binary data stream is received. A synchronization mark having at least one isolated peak is generated into at least one point in the data stream. An encoded data stream is formed by concatenating the synchronization mark with the received binary data. During decoding, the synchronization mark is detected based on error propagation occurring adjacent to the at least one isolated peak of the synchronization mark.

Abstract: Channel parameters for a magnetic readback channel are optimized by detecting a readback signal that is recorded on a magnetic medium. The readback signal contains a plurality of predetermined-length control fields. Each control field is arranged between two user data fields and contains at least one transition. At least one selected readback parameter, such as a frequency of a readback channel system clock, a gain of the readback channel, a equalization response of the readback signal, and/or an amplitude asymmetry of the readback channel, is optimized based on information contained in at least one control field.

Abstract: Provided is a method, system, and program for storing input groups of uncoded binary data on a storage medium. A plurality of uncoded data blocks in a data stream are received. An encoded data stream is obtained from concatenating successive encoded blocks such that the encoded data stream includes a predetermined bit pattern comprising a plurality of bits. The bit pattern always occurs within a first number of bits and two occurrences of a “1” or “0” occur within a second number of bits. The encoded data blocks are stored on the storage medium.

Abstract: Adjustment of a read detection equalizer filter of a magnetic tape drive is conducted utilizing a required control pattern signal which comprises a required portion of a normal recording format of the magnetic tape. An example comprises a data set separator signal. The sensed required control pattern signal is processed with respect to a target reference pattern signal to adapt the read detection equalizer filter to the target reference pattern signal.

Abstract: Adjustment of a read detection equalizer filter of a magnetic tape drive is conducted utilizing a required control pattern signal which comprises a required portion of a normal recording format of the magnetic tape. An example comprises a data set separator signal. The sensed required control pattern signal is processed with respect to a target reference pattern signal to adapt the read detection equalizer filter to the target reference pattern signal.

Abstract: A decoding circuit has a nonlinear equalizer which employs a signal conditioning algorithm for conditioning a partial response sampled signal to eliminate intersymbol interference. The inventive decoding circuit has an analog-to-digital converter for sampling an analog signal, a linear equalizer for adjusting the amplitude and phase relations of the sampled signal, a nonlinear equalizer for conditioning the sampled signal and outputting a partial response sampled signal having two nonzero samples, and a partial response maximum likelihood detector, for detecting the partial response sampled signal having two nonzero samples.

Abstract: Provided is a method, system, and program for storing input groups of uncoded binary data on a storage medium. A plurality of uncoded data blocks in a data stream are received. An encoded data stream is obtained from concatenating successive encoded blocks such that the encoded data stream includes a predetermined bit pattern comprising a plurality of bits. The bit pattern always occurs within a first number of bits and two occurrences of a “1” or “0” occur within a second number of bits. The encoded data blocks are stored on the storage medium.

Abstract: Provided is a method, system, and program for providing synchronization in a binary data stream. A binary data stream is received. A synchronization mark having at least one isolated peak is generated into at least one point in the data stream. An encoded data stream is formed by concatenating the synchronization mark with the received binary data. During decoding, the synchronization mark is detected based on error propagation occurring adjacent to the at least one isolated peak of the synchronization mark.

Abstract: A decoding circuit has a nonlinear equalizer which employs a signal conditioning algorithm for conditioning a partial response sampled signal to eliminate intersymbol interference. The inventive decoding circuit has an analog-to-digital converter for sampling an analog signal, a linear equalizer for adjusting the amplitude and phase relations of the sampled signal, a nonlinear equalizer for conditioning the sampled signal and outputting a partial response sampled signal having two nonzero samples, and a partial response maximum likelihood detector, for detecting the partial response sampled signal having two nonzero samples.

Abstract: A timing recovery system encodes data while impressing recognizable patterns thereon, enabling precise timing during subsequent readback operations. An uncoded binary sequence is encoded using an m/n rate block coded sequence, incorporating a unique predetermined binary bit pattern that occurs with a selected level of frequency. The encoded sequence is stored on the recording medium as a series of flux transitions. To read back the stored data, a read head measures the flux transitions stored on the medium and generates a representative analog waveform. A sampler samples the waveform in accordance with a timing scheme provided by a timing circuit. The timing circuit adjusts the timing of the samples to ensure that the analog waveform is sampled at appropriate times to yield the most accurate results. The timing circuit evaluates two consecutive samples to identify samples associated with features of the analog readback waveform that corresponds to the predetermined bit patterns.

Abstract: The present invention is a data detection channel with improved detection reliability and better immunity to signal dropout and noise, that has reduced data redundancy. The data detection channel includes a preamp/filter, a sample/quantizer, an equalizer, a timing recovery circuit and a digital detection filter. The digital detection filter includes a finite impulse response filter, a synchronization and windowing device and a data detection circuit. The a finite impulse response filter has a plurality of coefficients and stores a plurality of channel data samples. On each cycle of the sampling clock, the finite impulse response filter is operable to input and store a channel data sample and output a sum signal representing a sum of each product of each coefficient multiplied by a corresponding stored channel data sample. The synchronization and windowing device is operable to receive the sum signal each sampling clock cycle and output the sum signal, if it corresponds to a symbol.

Abstract: The present invention is an encoder and decoder that eliminate all infinitely propagating error sequences for many sets of taps. The encoder includes an input circuit operable to receive an unencoded data signal and an encoding circuit, coupled to the input circuit, operable to generate the encoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel. The decoder includes an input circuit operable to receive an encoded data signal and a decoding table, coupled to the input circuit, operable to generate the decoded data signal using a code that eliminates infinitely propagating error sequences when the encoded data signal is recovered by a decision feedback equalizer data recovery channel.

Abstract: A method and apparatus for the recovery of information via asynchronous signal sampling of coded analog waveforms by double interpolating values into the train of asynchronously sampled signals prior to the train being applied to a synchronous detector. The double interpolation includes averaging successive sample signals and midpoint interpolating them between the sample, and then interpolating signals between the sample signals and midpoint signals closest to predicted synchronous points. This double interpolation facilitates low sampling rates while still effectuating accurate synchronous digital detection.

Abstract: A hard disk drive read circuit for d=1 run length limited (RLL) encoded data which processes multiple consecutive data samples in parallel. The circuit of the present invention receives an analog signal from the read head of the hard disk drive. The circuit comprises a plurality of digital detection channels, coupled to the analog signal, each channel outputting an alternate bit of digital data represented by the analog signal. A timing circuit, coupled to the plurality of digital detection channels, generates a plurality of timing signals controlling the plurality of digital detection channels. The timing circuit derives timing information from one of the digital detection channels. The d=1 RLL code is modified so that there are at most nine consecutive 0's in the digital data output by the digital detection channel from which the timing circuit derives the timing information. An encoder generates the encoded digital data to be recorded on the hard disk drive.

Abstract: A method and apparatus for decoding a partial response encoded signal to generate a decoded signal. The first stage of the apparatus, a first delay filter, receives the partial response encoded signal and filters it with a delay characteristic of (1-D.sup.2)(1+D). The second stage, a timing system, generates a digital signal representative of the first filtered signal. The timing system includes an equalizer with an EPR4 equalization characteristic. The third stage, a second delay filter, filters the signal with a delay characteristic of 1-D. The final stage, a partial Viterbi decoder, generates the decoded signal.