Patents by Inventor Constantin Papadas
Constantin Papadas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6521942Abstract: The present invention relates to a method of manufacturing an electrically programmable memory cell with a lateral floating gate with respect to the control gate, including the steps of forming an insulated control gate on an active area; forming a thin insulating layer around the control gate; successively depositing a thin layer of a conductive material and a layer of an insulating material; anisotropically etching the insulating material to form spacers of this material; and removing the portions of the thin conductive layer which are not coated with the spacers.Type: GrantFiled: August 10, 2001Date of Patent: February 18, 2003Assignee: STMicroelectronics S.A.Inventors: Joseph Borel, Jean-Pierre Schoellkopf, Constantin Papadas
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Patent number: 6465332Abstract: The invention is directed to a method of manufacturing an area of a first type of conductivity extending a depth into a semiconductor substrate and having a doping gradient as a function of the depth into the semiconductor substrate. The method comprises acts of providing a semiconductor substrate of the first type of conductivity; implanting nitrogen in an upper surface of the semiconductor substrate, with a dose in a range of between approximately 5.1013 and 5.1015 at./cm2, annealing the semiconductor substrate; and growing an epitaxial layer on the substrate of the first type of conductivity having a doping level lower than the semiconductor substrate.Type: GrantFiled: January 10, 2000Date of Patent: October 15, 2002Assignee: STMicroelectronics S.A.Inventors: Constantin Papadas, Jorge L. Regolini, Thomas Skotnicki, André Grouillet, Christine Morin
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Publication number: 20020001903Abstract: The present invention relates to a method of manufacturing an electrically programmable memory cell with a lateral floating gate with respect to the control gate, including the steps of forming an insulated control gate on an active area; forming a thin insulating layer around the control gate; successively depositing a thin layer of a conductive material and a layer of an insulating material; anisotropically etching the insulating material to form spacers of this material; and removing the portions of the thin conductive layer which are not coated with the spacers.Type: ApplicationFiled: August 10, 2001Publication date: January 3, 2002Inventors: Joseph Borel, Jean-Pierre Schoellkopf, Constantin Papadas
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Patent number: 6297093Abstract: The present invention relates to a method of manufacturing an electrically programmable memory cell with a lateral floating gate with respect to the control gate, including the steps of forming an insulated control gate on an active area; forming a thin insulating layer around the control gate; successively depositing a thin layer of a conductive material and a layer of an insulating material; anisotropically etching the insulating material to form spacers of this material; and removing the portions of the thin conductive layer which are not coated with the spacers.Type: GrantFiled: March 25, 1999Date of Patent: October 2, 2001Assignee: STMicroelectronics S.A.Inventors: Joseph Borel, Jean-Pierre Schoellkopf, Constantin Papadas
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Patent number: 6218700Abstract: A remanent, electrically programmable and erasable, memory device comprises of a MOS type transistor whose gate insulator contains charged mobile species is disclosed. The gate insulator is comprised transversely of a sandwich comprising at least five areas. Two intermediate areas have first band-gap values, and two endmost and a central areas have band gap values greater than the first values.Type: GrantFiled: October 28, 1998Date of Patent: April 17, 2001Assignee: STMicroelectronics S.A.Inventor: Constantin Papadas
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Patent number: 6144257Abstract: The present invention relates to a bus control buffer amplifier. The output terminal is associated with a first pull-down N-channel MOS transistor and with a second pull-up N-channel MOS transistor. The first N-channel MOS transistor is directly controlled by an input signal. The second MOS transistor is an N-channel transistor, and its gate is controlled by a third pull-down N-channel MOS transistor directly controlled by the input signal, and by a fourth pull-up N-channel MOS transistor, which is controlled by the inverted input signal. The fourth N-channel MOS transistor has a very abrupt drain-substrate junction.Type: GrantFiled: February 24, 1998Date of Patent: November 7, 2000Assignee: SGS-Thomson Microelectronics S.A.Inventors: Ilias Bouras, Constantin Papadas, Jean-Pierre Moreau
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Patent number: 6051884Abstract: The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.Type: GrantFiled: July 17, 1998Date of Patent: April 18, 2000Assignee: SGS-Thomson Microelectronics S.A.Inventor: Constantin Papadas
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Patent number: 6018475Abstract: The present invention relates to the use of a conventional MOS transistor as a memory point in which, during programming, the well of the MOS transistor is connected to a reference potential, the drain and the source are connected to a current source adapted to bias the drain and source junctions in reverse and in avalanche so that the space charge region extends along the entire channel length, the gate is set to the reference potential if the memory point does not have to be programmed and to a distinct potential if the memory point has to be programmed; and during the reading, circuitry is provided to detect a high or low impedance state between the gate and the well.Type: GrantFiled: October 15, 1998Date of Patent: January 25, 2000Assignee: STMicroelectronics S.A.Inventors: Constantin Papadas, Jean-Pierre Schoellkopf
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Patent number: 5903494Abstract: A four state programmable memory cell includes a substrate of a first conductivity type having a channel region having a first side and a second side, a control gate located on a first insulating layer above the channel region, a drain region of a second conductivity type located on the substrate adjacent to the first side of the channel region, a source region of a second conductivity type located on the substrate adjacent to the second side of the channel region, a first insulated floating gate located on a second insulating layer above the drain region adjacent to the control gate, and a second insulated floating gate located on a third insulating layer above the source region adjacent to the control gate.Type: GrantFiled: November 19, 1997Date of Patent: May 11, 1999Assignee: SGS-Thomson Microelectronics S.A.Inventors: Constantin Papadas, Bernard Guillaumot
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Patent number: 5851919Abstract: The invention provides a method for producing wiring and contacts in an integrated circuit including the steps of forming insulated gate components on a semiconductor substrate; applying a photo-reducible dielectric layer to cover the substrate; etching holes and forming contacts; photo-reducing the dielectric to increase its conductivity; covering the resulting structure with an interconnect layer; etching the interconnect layer to define wiring in electrical contact with the contacts; and oxidizing the dielectric to reduce its conductivity.Type: GrantFiled: May 6, 1997Date of Patent: December 22, 1998Assignee: SGS-Thomson Microelectronics S.A.Inventor: Constantin Papadas
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Patent number: 5740103Abstract: An electrically programmable cell comprises a substrate of the first conductivity type having a channel region, a control gate on a first insulating layer above the channel region, a source region and a drain region of a second conductivity type, on both sides of the channel region, at least the drain region including a low-doped region adjacent to the channel, a floating gate on a second insulating layer above at least a portion of said low-doped region. The thickness of the second insulating layer is lower than the thickness of the first insulating layer and is low enough for having charge transfers through tunnel effect.Type: GrantFiled: March 6, 1997Date of Patent: April 14, 1998Assignee: SGS-Thomson Microelectronics S.A.Inventors: Constantin Papadas, Bernard Guillaumot
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Patent number: 5687113Abstract: An electrically programmable cell comprises a substrate of the first conductivity type having a channel region, a control gate on a first insulating layer above the channel region, a source region and a drain region of a second conductivity type, on both sides of the channel region, at least the drain region including a low-doped region adjacent to the channel, a floating gate on a second insulating layer above at least a portion of said low-doped region. The thickness of the second insulating layer is lower than the thickness of the first insulating layer and is low enough for having charge transfers through tunnel effect.Type: GrantFiled: March 28, 1995Date of Patent: November 11, 1997Assignee: SGS-Thomson Microelectronics S.A.Inventors: Constantin Papadas, Bernard Guillaumot