Abstract: A package for interconnecting a plurality of integrated circuit chips into a functional unit comprising a multilayer substrate having ground and power conducting layers and a frame for holding the chips with their terminal pads on the side of the frame opposite the substrate. Power and ground terminal pads on the chips are coupled to the appropriate potentials via registering conductive feedthroughs passing through the frame and into the substrate into contact with appropriate power or conductive layers in the substrate. Signal pads on the chips are interconnected by means of a conductive layer which is located over the chips on the side of the frame opposite the substrate.

Abstract: A method for fabricating a composite semiconductor from a plurality of substantially identical individual semiconductor devices formed on a common semiconductor wafer includes testing the devices on the wafer to generate a positional mapping of acceptable and non-acceptable devices, dividing the wafer into a plurality of areas of arbitrary size, connecting corresponding contact pads on only the acceptable devices within a given area to each other via common conductive paths which are supported on a dielectric film covering the pads, the film having appropriately located holes filled with conductive material to electrically couple the common conductive paths and the underlying contact pads of only the acceptable devices. The devices within a given area are intercoupled in a manner to form an operational array; single or multiple arrays may be coupled together to form a composite package having common external contacts and heat sink supports.

Abstract: Multilayer circuit boards composed primarily of silicon and containing buried ground planes and buried conducting runs are fabricated in one embodiment by positioning conductive patterns (12) on the surfaces of silicon substrates and melting a solder component of the conductive patterns (12) and allowing it to flow together with solder from the conductive patterns (12) on a stacked, adjacent silicon substrate (10). When the solder cools, a single conductive pathway (18) exists between adjacent silicon substrates (10) and bonds the adjacent substrates. If the substrates are coated with SiO.sub.2 (20), a multilayer structure with buried microwave strip lines (22) is formed in the bonding process. Alternatively, highly resistive silicon substrates (26) are used as a dielectric for microwave strip lines (24) on a top surface thereof and a conductive sheet (28) on the bottom surface thereof acts as a ground plane for microwave energy propagating along strip line (24).

Abstract: A hybrid integrated circuit chip package is disclosed which includes a hybrid, low loss, multilayer metallization, silicon printed wiring board as an interconnecting, two-sided module to reduce the length of interconnections between integrated circuit chips positioned on opposite sides of the module.

Abstract: Solder layers in a semiconductor chip package, which electrically interconnect conductors used to gain electrical access to the electrodes on the semiconductor chip, are subjected to a transverse compressive force in excess of about 2 pounds per square inch. The semiconductor chip package can thereby undergo a marked increase in the number of cycles of heating and cooling before it fails due to increased thermal resistance arising from structural degradation of the solder layers.

Abstract: A method for depositing gold bumps on metallized pads of semiconductor chips uses a commercially available thermocompression or thermosonic gold wire bonder. The method includes the steps of depositing a gold ball with an attached wire on the metallized pad, and removing the wire so that a gold bump remains on the pad.

Abstract: A hermetically sealed package for a power semiconductor wafer is provided comprising substantially entirely silicon materials selected to have coefficients of thermal expansion closely matching that of the power semiconductor wafer. A semiconductor wafer such as a power diode comprises a layer of silicon material having first and second device regions on respective sides thereof. An electrically conductive cap and base, each including a layer of silicon material, are disposed in electrical contact with the first and second regions of the semiconductor device, respectively. An electrically insulative sidewall of silicon material surrounds the semiconductor wafer, is spaced from an edge thereof, and is bonded to the cap and base for hermetically sealing the package. An electrical passivant is disposed on an edge of the semiconductor wafer adjoining the first and second device regions for preventing electrical breakdown between the cap and base.

Abstract: Hermetic power chip packages are constructed in building block form to reduce the cost of electrical testing of power chips. The power chip packages utilized dielectric plates with metallic sheets bonded to the dielectric plates. Electric access to at least selected terminals of a power chip is gained through one of the dielectric plates by including holes through the plates which are filled with a conductive medium. One form of the hermetic package includes a gasket with a thermal expansion coefficient close to that of a dielectric plate of the hermetic package and thereby results in a high level of package durability even after repeated cycling of the package between widely differing hot and cold temperatures.

Abstract: A thyristor packaging system utilizes structured metal, strain buffers to provide paths of high electrical and thermal conductivity from the anode and cathode of a thyristor to power conductors connected to the anode and the cathode, such strain buffers each comprising a bundle of substantially parallel, closely packed strands of metal wire.

Abstract: Reconstituted metal oxide varistors are formed by hot pressing powdered metal oxide varistor ceramic with plastic resin. Metal electrodes may be pressed directly into the ceramic-plastic composite to provide improved contact characteristics.

Abstract: A direct bond between metallic members and non-metallic members is achieved at elevated temperatures in a controlled reactive atmosphere without resorting to the use of electroless plating, vacuum deposition or intermediate metals. A metal member such as copper, for example, is placed in contact with a non-metallic substrate, such as alumina, the metal member and the substrate are heated to a temperature slightly below the melting of the metal, e.g., between approximately 1065.degree. and 1080.degree. C. for copper, with the heating being performed in a reactive atmosphere, such as an oxidizing atmosphere, for a sufficient time to create a copper-copper oxide eutectic melt which, upon cooling, bonds the copper to the substrate. Various metals, non-metals and reactive gases are described for direct bonding.