Abstract: Apparatus for data entry and error detection of digital information. Data ocked into a register undergoes a correlation comparison against a data word already stored within the comparator circuit and a convolution check in which the bits of the data word are compared with each other in a predetermined order. If the input data satisfies these tests, the data word is placed in memory where it may be acted upon by other devices.

Abstract: A self-synchronized apparatus for recognizing identifying codes especially n missiles and spacecraft. The apparatus comprises a video quantizer for receiving bipolar video input signals and providing an output of validly timed data to a decode register which is clocked by a free running oscillator. The decode register defines a valid mark as "K" high bits followed by "K" low bits where 2K is the capacity of the decode register. A constant width decoder compares the first K bits in a sequential, pairwise fashion with the inverse of the values of the second K bits. The constant width decoder ANDs the pairwise comparison outputs to insure that "K" high bits are followed by "K" low bits before a "mark" signal is produced. A derivative data buffer receives the "mark" signals. A synchronous counter is coupled to the derivative buffer and the free running oscillator to produce one output pulse for every N oscillator output pulses.

Abstract: The present invention relates to method and apparatus for performing miss identification (MID) and decoding messages communicated to an identified missile without the use of a synchronous internal clock.